TSW-125-22-G-RA Datasheet| | | | Limits | | | Symbol | Parameter | Test conditions | Min | Typ | Max | Unit | | V (BR) DSS | Drain-source breakdown voltage | ID = ImA, VGs = OV | 600 | | | v | | V (BR) GSS | Gate-source breakdown voltage | IG = +100ccA, VDS = OV | ±30 | | | v | | IGSS | Gate-source leakage current | VGS = +25V, VDS = OV | | | ±10 | | | IDSS | Drain-source leakage current | VDS = 600V, VGS = OV | | | 1 | mA | | VGS (th) | Gate-source threshold voltage | ID = 1rTiA, VDS = 10V | 2 | 3 | 4 | v | | rDS (ON) | Drain-source on-state resistance | ID = 7A, VGS = 10V | | 0 46 | 0.60 | | | VDS (ON) | Drain-source on-state voltage | ID = 7A, VGS = 10V | | 3 2 | 4 2 | v | | yfs | Forward transfer admittance | ID = 7A, VDS = 10V | 6 0 | 9 0 | | S | | Ciss | Input capacitance | | | 2100 | | pF | | Coss | Output capacitance | VDS = 25y VGS = Oy f= 1MHz | | 250 | | pF | | Crss | Reverse transfer capacitance | | 40 | | pF | | td (on) | Turn-on delay time | | | 40 | | ns | | tr | Rise time | VDD = 200V ID = 7A, VGS = 10V, RGEN = RGS = sol | | 60 | | ns | | td (off) | Turn-off delay time | | 200 | | ns | | tf | Fall time | | 70 | | ns | | VSD | Source-drain voltage | Is = 7A, VGS = OV | | 1 5 | 2 0 | v | | Rth (ch-c) | Thermal resistance | Channel to case | | | 0 50 | IC/W | | | | | | | |
TSW-125-22-G-RA Price| | SYMBOLS | FR 201G | FR 202G | FR 203G | FR 204G | FR 205G | FR 206G | FR 207G | UNIT | | Maximum Repetitive Peak Reverse Voltage | VRRM | 50 | 100 | 200 | 400 | 600 | 800 | 1000 | Volts | | Maximum RMS Voltage | VRMS | 35 | 70 | 140 | 280 | 420 | 560 | 700 | Volts | | Maximum DC Blocking Voltage | VDC | 50 | 100 | 200 | 400 | 600 | 800 | 1000 | Volts | | Maximum Average Forward Rectified Current, 0.375" (9.5mm) lead length At Te = 550C | I(AV) | 2.0 | Amps | | Peak Forward Surge Current 8.3mS single half sine wave superimposed on rated load (JEDEC method) | IFSM | 70 | Amps | | Maximum Instantaneous Forward Voltage @ 2.OA | VF | 1.3 | Volts | | Maximum DC Reverse Current at Rated TA = 25 0C | IR | 5.0 | | | DC Blocking Voltage per element TA = 125 0C | 500 | LLA | | Maximum Reverse Recovery Time Test conditions Jr = 0.5A. ID - 1 .OA. JDD - 0 75A | trr | 150 | 250 | 500 | nS | | Typical Junction Capacitance (Measured at l.OMHz and applied reverse voltage of4.OV) | cJ | 20 | pF | | Typical Thermal Resistance (Note l) | ROJA | 40 | OC/W | | Operating Junction Temperature Range | TJ | (-65 to +175) | OC | | Storage Temperature Range | TSTG | (-65 to +175) | oC | | | | | | | | | | |
TSW-125-22-G-RA on stock For surface mount environments ST provides a Chip Set solution consisting of a 28 pin 330mil SOIC NVRAM Supervisor (M402300) and a 32 pin TSOP Type 11 (10 x 20mm) LPSRAM (M682512) packages. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC pack- age after the completion of the surface mount pro- cess. Insertion of the SNAPHAT housing after reflow prevents potential battery damage due to the high temperatures required for device surface- mounting. The SNAPHAT housing is keyed to pre- vent reverse insertion. | Parameter | Name | Description | Min | Typ. | Max | Unit | | | Duty Cycle[2] = t2 X/ tl | Measured at l.5V | 40.0 | 50.0 | 60.0 | % | | t3 | Rise Time[2] | Measured between 0.8V and 2.OV | | | 1.50 | ns | | t4 | Fall Time[2] | Measured between 0.8V and 2.OV | | | 1.50 | ns | | t5 | Output to Output Skew[2] | All outputs equally loaded | | | 100 | ps | | t6 | Propagation Delay, BUF_IN Rising Edge to OUTPUT Rising Edge[2l | Measured at VDD/2 | 2.5 | 3.5 | 5 | ns | | | | | | | |
|
