The non-overlap time is realized with an adaptive non-overlap circuit (ANT). By using an adaptive non-overlap circuit, the application can determine the duration of the non-overlap time and make it optimum for each frequency (see Fig.4). The non-overlap time is determined by the slope of the half-bridge voltage, and is detected by the signal across resistor R16 which is connected directly to pin ACM. The minimum non-overlap time is internally fixed. The maximum non-overlap time is internally fixed at approximately 25% of the bridge period time. An internal filter of 30 ns is included at the ACM pin to increase the noise immunity.
TPS3123J12DBVRG4 on stock| Parameters | 403DMQ | Units | Conditions |
| VFM Max. Forward Voltage Drop | 0 87 | v | @ 200A | T= 25 0C |
| (Per Leg) (1) | 1 06 | V | @ 400A |
| 0 72 | V | @ 200A | Ti= 125 0C |
| 0 86 | v | @ 400A |
| IRM Max. Reverse Leakage Current | 6 | mA | T= 25 0C | |
| (Per Leg) (1) | 140 | mA | Ti= 125 0C | VR= rated VR |
| CT Max. Junction Capacitance (Per Leg) | 5500 | pF | VR = 5VDC, (test signal range 100Khz to lMhz) 250C |
| Ls Typical Series Inductance (Per Leg) | 5 0 | nH | From top of terminal hole to mounting plane |
| dv/dt Max. Voltage Rate of Change (Rated VR) | 10000 | VUS | |
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Oscillation: To test RF characteristics, this module is put on a fixture with two bias decoupling capacitors each on gate and drain a 4.700 pF chip capacitor, located close to the module, and a 22 pF (or more) electrolytic capacitor. When an amplifier circuit around this module shows oscillation, the following may be checked: a) Do the bias decoupling capacitors have a low inductance pass to the case of the module? b) Is the load impedance ZL=50Q? c) Is the source impedance ZG=50Q?
