| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact |
TPS310333DVBR Datasheet
TPS310333DVBR Price Power sensing is implemented with the PWR SEN and PWR REF lines. The outputs of these pins are transistor collec- tors and need to be pulled up to the supply through a resistor. PWR REF provides an output current proportional to the output stage bias current, and PWR SEN provides an output current proportional to the total (RF and bias) current of the output stage. The pull-up resistors convert these currents to voltages, and the voltage difference between these two pins is proportional to the RF current. See the graph, "VREF-VSENSE versus POUT", for the response of this signal. This differ- ence signal can be fed to a power control circuit elsewhere in the end product, or it can be processed at the PA with addi- tional circuitry and used to adjust the VREG voltage(s) to implement automatic level control. Contact RFMD Sales or Applications Engineering for additional data and guidance in using this feature. TPS310333DVBR on stock
NOTES: 1. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output. 2. This set-up time defines the amount of time prior to the input signal the delay tap of the device must be set. 3. This set-up time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than +75mV to that IN/IN transition. 4. This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output response greater than +75mV to that IN/IN transition. 5. This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets the specified IN to Q propagation delay and transition times. 6. Specification limits represent the amount of delay added with the assertion ofeach individ ual delay control pin. The various combinations ofasserted delay control inputs will typically realize Do resolution steps across the specified programmable range. 7. The linearity specification guarantees to which delay control input the programmable steps will be monotonic (i.e. increasing delay steps for increasing binary counts on the control inputs Dn). Typically, the device will be monotonic to the Do input, however, under worst case conditions and process variation, delays could decrease slightly with increasing binary counts when the Do input is the LSB. With the Di input as the LSB, the device is guaranteed to be monotonic over all specified environmental conditions and process variation. 8. The jitter of the device is less than what can be measured without resorting to very tedious and specialized measurement techniques. |
|||||||||||||||||||||
