TPS301DR Datasheet| Address (x32 Mode) | Address (x16 Mode) | Data | Description | | | | 3h or 4h | Number of Erase Block Regions within device | | 3h | For Flash Part Numbers: Am29BDD160GX54CYZ, Am29BDD160GX65DYZ, Am29BDD160GX64CYZ, and Am29BDD160GX65AYZ, where X, Y, and Z reflect user selectable options, i.e. X = Boot Sector, Y = Package, Z = Temperature | | 2Ch | 58h | 4h | For Flash Part Numbers: Am29BDD160GX80CYZ, Am29BDD160GX90AYZ, and Am29BDD160GB- DS3/4/5/6/7, where X, Y, and Z reflect user selectable options, i.e. X = Boot Sector, Y = Package, Z = Temperature. These part numbers are obsolete and are replaced by the above parts | | | | |
TPS301DR Price| FREQUENCY | S | l | S21 | S | 2 | S22 | | MHz | MAG | ANG | MAG | ANG | MAG | ANG | MAG | ANG | | 1000 0000 | 0.978 | -25.5 | 3.020 | 157 3 | 0.042 | 71 7 | 0 741 | -14.5 | | 2000 0000 | O928 | -50.3 | 2.868 | 136 6 | 0.078 | 56 9 | 0 702 | -28.1 | | 3000 0000 | O872 | -74.4 | 2.696 | 116 9 | 0.107 | 42 4 | 0 649 | -41.4 | | 4000 0000 | O810 | -97.8 | 2.468 | 97.8 | 0.124 | 29 5 | 0 585 | -53.9 | | 5000 0000 | O758 | -119.5 | 2.241 | 80.9 | 0.134 | 18 1 | 0 529 | -66.4 | | 6000 0000 | O729 | -140.1 | 2.046 | 64 5 | 0.138 | 8 1 | 0 480 | -79.5 | | 7000 0000 | O704 | -157.7 | 1.829 | 49 3 | 0.134 | -O.l | 0 446 | -92.7 | | 8000 0000 | O701 | -172.8 | 1.661 | 36 0 | 0.127 | -5.1 | 0 429 | -106.3 | | 9000 0000 | O701 | 173.2 | 1.509 | 23 1 | 0.121 | -9.2 | 0 423 | -120.2 | | 10000 0000 | 0.705 | 160.4 | 1.370 | 10 7 | 0.115 | -12.4 | 0 422 | -13 5.1 | | 11000.0000 | O720 | 149.0 | 1.255 | -0.9 | 0.109 | -12.6 | 0 434 | -150.1 | | 12000 0000 | 0.733 | 13 8.5 | 1.134 | -12.8 | 0.102 | -12.4 | 0 458 | -164.3 | | 13000 0000 | 0.750 | 131.2 | 1.007 | -22.3 | 0.100 | -9.6 | 0 495 | -177.4 | | 14000 0000 | 0.777 | 122.8 | 0.929 | -32.1 | 0.104 | -7.3 | 0 535 | 170 6 | | 15000 0000 | 0.785 | 115.3 | 0.836 | -41.2 | 0.109 | -6.5 | 0 577 | 160 0 | | 16000 0000 | 0.799 | 108.0 | 0.763 | -49.6 | 0.118 | -7.0 | 0 610 | 149 5 | | | | | | | | | |
TPS301DR on stock FEATURES JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS Latency (2 & 3) -. Burst Length (1, 2, 4, 8) -. Burst Type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock. Burst Read Single-bit Write operation DQM for masking Auto & self refresh 64ms refresh period (4K cycle) .476 .492 .533 .577 .596 .583 .578 .647 .881 1.06 1.18 1.13 .946 .559 .345 .235 .173 .134 .108 .089 .075 .065 .057 .042 .033 .026 .021 .018 .015 .011 .007 .005 .004 .003 .002 .002
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