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TPS2543814133 Datasheet

PIN	CONNECTION
l	CATHODE A
2	NO PIN
3	ANODEB
4	CATHODE B
5	NO CONNECTION
6	ANODEA

TPS2543814133 Price

A Warm Reset means that the host resets the device by using the /RP pin. When the a /RP low is issued, the device logic stops a current operations and executes internal reset operation and resets current NAND Flash core operation synchronized with the falling edge of /RP.
TPS2543814133 on stock

				I I 60Hz Resistive
L= - Leaa uengtns	0.375	(9.5mn	L		r Inducl	ive Loa	d I l<c)
							u/ u-?
						0.8 x 0.8 x 0.040"
						(2C	x 20 x lmrTl)
				j		Co	Jper Heat Sinks
				j
					j

Pin	unction	Description	Interface Schematic
1	VCC1	First stage collector supply. A low frequency decoupling capacitor (e.g., 1 F) is required.
2	RF IN	RF input internally matched t0 50 I . This input is internally AC-coupled.
3	VREG	Regulated voltage supply for amplifier bias. In Power Down mode, both VREG and VMODE need to be LOW(<0.5V).
4	VMODE	For nominal operation (High Power Mode), VMODE iS set LOW. When set HIGH, devices are turned off to improve efficiency.
5	VCC2	Output stage collector supply. A low frequency decoupling capacitor (e.g., 1 F) is required.
6	RF OUT	RF output internally matched t0 50 I . This output is internally AC-coupled.
7	GND	Ground connection. Connect to package base ground. For best perfor- mance, keep traces physically short and connect immediately to ground plane.
Pkg Base	GND	Ground connection. The backside of the package should be soldered to a top side ground pad which is connected to the ground plane with mul- tiple vias. The pad should have a short thermal path to the ground plane.

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