| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact |
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TPIC6B273DWRG4 (PB FREE) Datasheet co Build in Biasing Circuit; To reduce using parts cost & PC board space. co Low noise; NF = 1.0 dB typ. at f= 200 MHz,NF =1.75 dB typ. at f=900 MHz co High gain; PG = 30 dB typ. at f= 200 MHz, PG = 22 dB typ. at f= 900 MHz co Withstanding to ESD; Build in ESD absorbing diode. Withstand up t0 200 V at C = 200 pF, Rs = 0 conditions co Provide mini mold packages; CMPAK-4 (SOT-343mod) TPIC6B273DWRG4 (PB FREE) Price
TPIC6B273DWRG4 (PB FREE) on stock High Performance 16-bit CPU with 5-Stage Pipeline - 25 ns Instruction Cycle Time at 40 MHz CPU Clock (Single-Gycle Execution) - 1-Cycle Multiplication (16 x 16 bit), Background Division (32 / 16 bit) in 21 Cycles - 1-Cycle Multiply-and-Accumulate (MAG) Instructions - Enhanced Boolean Bit Manipulation Facilities - Zero-Gycle Jump Execution - Additional Instructions to Support HLL and Operating Systems - Register-Based Design with Multiple Variable Register Banks - Fast Context Switching Support with Two Additional Local Register Banks - 16 Mbytes Total Linear Address Space for Code and Data - 1024 Bytes On-Chip Special Function Register Area (C166 Family Compatible) 16-Priority-Level Interrupt System with 73 Sources, Sample-Rate down t0 50 ns 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC), 24-Bit Pointers Cover Total Address Space Clock Generation via on-chip PLL (factors l:0.15 ... 1:10), or via Prescaler (factors l:1 ... 60:1) On-Chip Memory Modules - 2 Kbytes On-Chip Dual-Port RAM (DPRAM) - 4 Kbytes On-Chip Data SRAM (DSRAM) - 6 Kbytes On-Chip Program/Data SRAM (PSRAM) - 256 Kbytes On-Chip Program Memory (Flash Memory) On-Chip Peripheral Modules - 12-Channel A/D Converter with Programmable Resolution (10-bit or 8-bit) and Conversion Time (down t0 2.55 U.s or 2.15 U.s) - Tw0 16-Channel General Purpose Capture/Compare Units (32 Input/Output Pins) - Multi-Functional General Purpose Timer Unit with 5 Timers - Two Synchronous/Asynchronous Serial Channels (USARTs) - Two High-Speed-Synchronous Serial Channels - On-Chip TwinCAN Interface (Rev. 2.OB active) with 32 Message Objects (Full GAN/Basic CAN) on Two CAN Nodes, and Gateway Functionality - IIC Bus Interface (10-bit addressing, 400 kbit/s) with 3 Channels (multiplexed) - On-Chip Real Time Clock, Driven by Dedicated Oscillator Idle, Sleep, and Power Down Modes with Flexible Power Management Programmable Watchdog Timer and Oscillator Watchdog (1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. |
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