| | Tinr | |
| etxclk | In | 104MHz transmit byte clock. The Core samples all Utopia Transmit signals on txclk rising edge. |
| etxdata[15:0] | Out | Transmit data bus. The width of the data bus is 16 bit. Bit N is the MSB. |
| etxprty | Our | Transmit data bus parity. Standard odd or non-standard even parity can be optionally checked by the connected Slave. When the parity check is disabled during the Core configuration, or not used in the design, the pin txprty should be left open. |
| etxsoc | Out | Transmit start of cell. Asserted by the Master to indicate that the current word is the first word of a cell. |
| etxenb | Out | Active low transmit data transfer enable. |
| etxclav[0] | ln | Cell buffer available. Asserted in octet level transfers to indicate to the Master that the FIFO is almost full (Active low) or, in cell level transfers, to indicate to the Master that the PHY port FIFO has space to accept one cell. |
| etxclav[3:1] (0) | ln | Extra FIFO Full / Cell buffer available. In MPHY mode and when direct status indication is selected during the Core configuration, one txclav signal is implemented per PHY port. The maximum number of clav signals is limited to fou r. |
| etxaddr[4:0] | Out | Utopia transmit address. When the Core operates in MPHY mode, address bus used during polling and slave port selection. Bit 4 is the MSB. txaddr(4:0) becomes optional (And should be left open) when the Core does not operate in MPHY mode. |
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