| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact |
TPCS8208 TE12L Datasheet
TPCS8208 TE12L Price
TPCS8208 TE12L on stock Shift right is accomplished on the high-to-low transi- tion of clock l when the mode control is low; shift left is accomplished on the high-to-low transition of clock 2 when the mode control is high by connecting the output of each flip-flop to the parallel input of the previous flip-flop (QD to input C. etc.) and serial data is entered at input D. The clock input may be applied commonly to clock l and clock 2 if both modes can be clocked from the same source. Changes at the mode control input should normally be made while both clock inputs are low; however, conditions described in the last three lines of the function table will also ensure that register contents are protected. The data on the DIN input is loaded into the shift register on therising edgeof theclock. TheMSBisloaded first. The DAC register loads the data from the shift register when CS/LD is pulled high. The CLKis disabled internally when CS/LD is high. Note: CLK must be low before CS/LD is pulled low to avoid an extra internal clock pulse. |
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