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The Philips FZPTM CPLDs introduce the new patent-pending XPLATM (eXtended Programmable Logic Array) architecture. The XPLATM architecture combines the best features of both PLA and PALTM type structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. The XPLATM structure in each logic block provides a fast 8ns PALTM path with 5 dedicated product terms per output. This PALTM path is joined by an additional PLA structure that deploys a pool of 32 product terms to a fully programmable OR array that can allocate the PLA product terms to any output in the logic block. This combination allows logic to be allocated efficiently throughout the logic block and supports as many as 37 product terms on an output. The speed with which logic is allocated from the PLA array to an output is only 2.5ns, regardless of the number of PLA product terms used, which results in worst case tPD'S of only 10.5ns from any pin to any other pin. In addition, logic that is common to multiple outputs can be placed on a single PLA product term and shared across multiple outputs via the OR array, effectively increasing design density.
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