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To control the relay, a bias voltage is applied between the bias and common pins. This is typically a standard 5 Vdc TTL supply. The control and status lines are referenced to the common pin and are fufly TTL and CMOS compatible. Typically, the relay would interface with system logic, such as a load management center or a remote terminal of a 1553 data bus system. A logic high on the controf pin will turn the relay output on and a logic low will turn the relay output off. Toggling the control from high to low and back to high will reset the relay output in event that the short circuit or current overload trip has been activated. The flow status line will indicate a logic low when the output (load) current exceeds lo% of the rated current and a logic high when the output current is less than 2% or the rated current. The trip status line will indicate a logic low should the relay output automatically turn off due to a short circuit or current overload condition. It will remain low until the output is reset by pulling the control line Iow for 50 mS. The trip status line is normally high when the trip circuit has not been activated. The timing relationships for the status lines are shown in Figures 4 and 5.
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