| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact |
|
TP9180 Datasheet Boost High-Side Gate Drive f BST) Connect a flying bootstrap capacitor between LX and BST to provide the gate-drive voltage to the high-side n-channel DMOS switch. The capacitor is alternately charged from the internally regulated output-voltage VD and placed across the high-side DMOS driver. Use a O.1[JF, 16V ceramic capacitor located as close to the device as possible. TP9180 Price FEATURES I +2 A, 50 V Continuous Output Rating I Low rDScon) Outputs (270 mQ, Typical) I Programmable Mixed, Fast, and Slow Current-Decay M I SerialInterface Controls Chip Functions I Synchronous Rectification for Low Power Dissipation I Internal UVLO and Thermal-Shutdown Circuitry I Crossover-Current Protection TP9180 on stock CHO+ (Pin 4): Positive Input for Differential Channel 0. CHO- (Pin 5): Negative Input for Differential Channel 0. CHl+ (Pin 6): Positive Input for Differential Channel l. CHl- (Pin 7): Negative Input for Differential Channel l. The voltage on these four analog inputs (Pins 4 t0 7) can have any value between GND and Vcc. Within these limits the conve rter bipolar input range (VIN = IN+- IN-) extends from -0.5 - (VREF) t0 0.5 - (VREF). Outside this input range the converter produces unique overrange and underrange output codes. GND (Pins 8, 9, 10, 15, 16): Ground. Multiple ground pins internally connected for optimum ground current flow and Vcc decoupling. Connect each one of these pins to a ground planethrough alowimpedance connection.AII five pins must be connected to ground for proper operation. CS (Pin 11): Active LOW Digital Input. A LOW on this pin enables the SDO digital output and wakes up the ADC. Following each conversion the ADC automatically enters the Sleep mode and remains in this low power state as
|
