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TP7340A-89 Datasheet

. High Voltage : VCEO = -120V . Excellent hFE Linearity : hFE (IC = -O.lmA) /hFE (IC = -2mA) =0.95 (Typ.) . High hFE : hFE=200700 . Low Noise : NF=ldB (Typ.), 10dB (Max.) * Complementary t0 2SC2713 . Small Package
TP7340A-89 Price

ltem		Symbol	Condition		Characteristics			Unit
ltem		Symbol	Condition		Min	Typ	Max	Unit
	Zero gate voltage collector current	ICES	VCE=1200V, VGE=OV				100	UA
	Gate-Emitter leakage current	IGES	VCE=OV, VGE=+20V				200	nA
	Gate-Emitter threshold voltage	VGE(th)	VCE=20V, lc=25mA		5 5	7.2	8 5	V
	Collector-Emitter saturation voltage	VCE(sat)	VGE=15V, lc=25A	chip		2.1		V
	Collector-Emitter saturation voltage	VCE(sat)	VGE=15V, lc=25A	terminal		2.2	2 6	V
n)	Input capacitance	Cies	VGE=OV, VCE=10V, f=lMHz			3000		pF
	Furn-on time	ton	Vcc=600V			0.35	1 2	US
	Furn-on time	tr	lc=25A			0.25	0 6
	Turn-off	toff	VGE=+15V			0.45	1 0
	Turn-off	tf	RG=51 1			0.08	0 3
	Forward on voltage	VF	IF=25A	chip		2 3		V
	Forward on voltage	VF	IF=25A	termi¨nal		2 4	3 2	V
	Reverse recovery time of FRD	trr	IF=25A				350	ns
	Zero gate voltage collector current	ICES	VCEs=1200V, VGE=OV				100	pA
	Gate-Emitter leakage current	IGES	VCE=OV, VGE=+20V				200	nA
	Collector-Emitter saturation voltage	VCE(sat)	lc=15A, VGE=15\	chip		2 1		V
	Collector-Emitter saturation voltage	VCE(sat)	lc=15A, VGE=15\	termi¨nal		2 2	2 6	V
	Turn-on time	ton	Vcc=600V			0.35	1 2	l_ls
	Turn-on time	tr	lc=15A			0.25	0 6
ca	Turn-off time	toff	VGE=+15V			0.45	1 0
	Turn-off time	tf	RG=821			0.08	0 3
	Reverse current	IRRM	VR=1200V				100	pA
	off-state current	IDM	VDM=1600V				1 0	mA
	Reverse current	IRRM	VRM=1600V				1 0	mA
	Gate trigger current	IGT	VD=6V, IT=IA				100	mA
	Gate trigger voltage	VGT	VD=6V, IT=IA				2 5	V
>	On-state voltage	VTM	ITM=25A	chip		1.05	1 15	V
-C l-	On-state voltage	VTM	ITM=25A	termi¨nal		1 1		V
	Forward on voltage	VFM	IF=25A	chip		1 1		V
	Forward on voltage	VFM	IF=25A	termi¨nal		1 2	1 5	V
O	Reverse current	IRRM	VR=1600V				100	pA
	Resistance	R	T=250C			5000		l
	Resistance	R	T=1000C		465	495	520	l
L	B value	B	T=25/500C		3305	3375	3450	K

TP7340A-89 on stock

Junction - ambient2)	Rth JA	725	K/W
Junction - soldering point	Rth Js	565	K/W

Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CEi, CE2, and CE3 are ALL asserted active, (3) the Write Enable input signal WE is deasserted HIGH, and 4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory array and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the output buffers. The data is available within 6.5 ns (133-MHz device) provided OE is active LOW. After the first clock of the read access, the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. On the subsequent clock, another operation (Read/Write/Deselect) can be initiated. When the SRAM is deselected at clock rise by one of the chip enable signals, its output will be tri-stated immediately.

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