TP3054WM-X COMBO Datasheet| Ambient Temperature: Tamb = 250C +50C . For VPP and Vcc Voltages refer to Programming Algorithm | | Parameter | Status | Symbol | Mln | Max | UnIts | Conditions | | Input Voltages | Logic "1" Logic "O" | VIH VIL | 2.0 0.1 | Vcc+l 0 8 | V V | | | Input Leakage | | 1L1 | -10 | 10 | UA | VIN = -O.1V to Vcc + 1.OV | | Output Vottages | Logic "1" Logic "O" | VOH VOL | 2.4 | 0.45 | V V | IOH = -2 mA IOL = 8 mA . | | Vcc Current, program & verify | | lcc | | 90 | mA | Notel | | VPP Current. program | | IPP | | 50 | mA | Notel | | A9 Product Identification | | VH | 11.5 | 12.5 | V | | | | | | | | |
TP3054WM-X COMBO Price| PT6701 | 5v | VID | | | PT6702 | 3.3V | VID | | | PT6705 | SV | Resistor | | | PT6715 | Sv | Resistor | | | PT6721 | 12V | VID | | | PT6725 | 12V | Resistor | | | | | |
TP3054WM-X COMBO on stock| Collector-emitter breakdown voltage Ic =1 mA | V(BR)CEO | 50 | | | V | | Collector-base breakdown voltage Ic = 100 cCA | V(BR)CBO | 50 | | | | Emitter-base breakdown voltage, IE = 10 c<A | V(BR)EBO | 3 | | | | Collector-base cutoff current VCB = 10 V, IE = 0 VCB = 35 V, IE = 0 VCB = 35 V, IE = 0, TA = 150 0C | ICBO | | | 1 0 50 20 | nA nA | | DC current gain Ic = 100 c<A, VCE = 5 V SMBT 5086 SMBT 5087 Ic = 1 mA, VCE = 5 V SMBT 5086 SMBT 5087 Ic = 10 mA, VCE = 5 V SMBT 5086 SMBT 5087 | hFE | 150 250 150 250 150 250 | | 500 800 | | | Collector-emitter saturation voltagei) Ic = 10 mA, IB = 1 mA | VCEsat | | | 0.3 | V | | Base-emitter saturation voltagei) Ic = 10 mA, lrB = 1 mA | VBEsat | | | 0.85 | | | | | | |
Notes: 1. Other operations except_for indicated this column are prohibited. 2. Do not apply CEf = VIL, CElr = VIL and CE2r = VIH all at once. 3. PSRAM Output Disable condition should not be kept longer than lms. 4. WE can be VIL if OE is VIL, OE at VIH initiates the write operations. 5. PSRAM LB,UB control at Read operation is not supported. 6. It is also used for the extended sector group protections. 7. The PSRAM Power Down Program can be performed one time after compliance of Power-UP timings and it should not be re- programmed after regular Read or Write. 8. PSRAM Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. IPDr current and data retention depends on the selection of Power Down Program. 9. Either or both LB and UB must be Low for PSRAM Read Operation. 10. Can be either VIL or VIH but must be valid before Read or Write. 11. See " PSRAM Power Down Program Key Table " located in the next page. 12. Protect " outer most " 2x8K bytes ( 4 words ) on both ends of the boot block sectors.
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