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TP155M025BRW Datasheet

Use only specialized low-ESR capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor's ESR will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. An aluminum electrolytic capacitor's ESR value is related to the case size with lower ESR available in larger case sizes. However, the equivalent series inductance (ESL) ofthese capacitors increases with case size and can reduce the useful- ness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor's imped- ance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size per- form better than a single large case capacitor.
TP155M025BRW Price

Standard Zener voltage tolerance is graded to the international E 24 (~5%) standard. Other voltage tolerances and higher Zener voltages on request. Die Toleranz der Zener-Spannung ist in der Standard-Ausfuhrung gestuft nach der internationalen Reihe E 24 (~5%). Andere Toleranzen oder hohere Arbeitsspannungen auf Anfrage.
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Pin Name	Pin No.	Functionality
RO+	1	Non-inverting output of the receive smoothing filter. This pin can typically drive a 2 kQ load to 1.575 volt peak referenced to the analog ground level.
RO+	2	Non-inverting output of the receive smoothing filter. This pin can typically drive a 2 kC) load to 1.575 volt peak referenced to the analog ground level.
PAI	3	This pin is the inverting input to the power amplifier. Its DC level is at the VAG voltage.
PAO-	4	Inverting power amplifier output. This pin can drive a 300 Q load t0 1.575 volt peak referenced to the VAG voltage level.
PAO+	5	Non-inverting power amplifier output. This pin can drive a 300 Q load t0 1.575 volt peak referenced to the VAG voltage level.
VDD	6	Power supply. This pin should be decoupled to Vss with a 0.1 UF ceramic capacitor.
FSR	7	8 kHz Frame Sync input for the PCM receive section. This pin also selects channel o or channel l in the GCI and IDL modes. It can also be connected to the FST pin when transmit and receive are synchronous operations.
PCMR	8	PCM input data receive pin. The data needs to be synchronous with the FSR and BCLKR pins.
BCLKR	9	PCM receive bit clock input pin. This pin also selects the interface mode. The GCI mode is selected when this pin is tied to Vss. The IDL mode is selected when this pin is tied to VDD. This pin can also be tied to the BCLKT when transmit and receive are synchronous operations.
PUI	1 0	Power up input signal. When this pin is tied to VDD, the part is powered up. When tied to VsS, the part is powered down.
MCLK	1 1	System master clock input supporting 2000 kHz only.
BCLKT	12	PCM transmit bit clock input pin.
PCMT	1 3	PCM output data transmit pin. The output data is synchronous with the FST and BCLKT pins.
FST	14	8 kHz transmit frame sync input. This pin synchronizes the transmit data bytes.
Vss	1 5	This is the supply ground. This pin should be connected to OV.
u/A-Law	16	Compander mode select pin.Law companding is selected when this pin is tied to VDD. A-Law companding is selected when this pin is tied to VsS.
AO	1 7	Analog output of the first gain stage in the transmit path.
Al-	1 8	Inverting input of the first gain stage in the transmit path.
Al+	1 9	Non-inverting input of the first gain stage in the transmit path.
VAG	20	Mid-Supply analog ground pin, which supplies a 2.5 Volt reference voltage for all-analog signal processing. This pin should be decoupled to Vss with a O.OIF t0 0.1F capacitor. This pin becomes high impedance when the chip is powered down.

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