| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact |
|
TP116 Datasheet The KM4164B contains 65,536 memory locations. Six- teen address bits are required to address a particular memory location. Since the KM4164B has only 8 address input pins, time multiplexed addressing is used to in put 8 row and 8 column addresses. The multiplexing is controlled by the timing relationship between the row add ress st robe {RAS), the column add ress st robe (CAS) and the valid address inputs. Operation of the KM4164B begins by strobing in a valid row address with RAS while CAS remains high. Then the address on the 8 address input pins is changed from a row address to a column address and is strobed in by CAS. This is the beginning of any KM4164B cycle in which a memory location is accessed. The specific type of cycle is determined by the state of the write enable pin and various timing relationships. The cycle is ter- minated when both RAS and ~AS have returned to the high state. Another cycle can be initiated after RAS re- mains high long enough to satisfy the RAS precharge time (tRP) requirement. TP116 Price This publication is issued to provide outline information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose or form part of any order or contract or be regarded as a representation relating to the products or services concerned. The Company reserves the right to alter without notice the specification, design, price or conditions of supply of any product or service. TP116 on stock
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||