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SCL (Pin l): Serial Clock Input. The 2-wire bus master fault conditions on the LTC1840. An external 10k pull-up device clocks this pin at a frequency between OkHz and is recommended. lOOkHz to enable serial bus communications. Data at the GPI01, GP102, GP103, GP104 (Pins 6, 7, 9, 10): General SDA pin is shifted in or out on rising SCL edges. SCL has iuts/0 utputs. These pins can be used as digital a logic threshold of lV and an external pull-up resistor or Pnuprupt9seitnhpCuL current source is normally required. CMOS logic thresholds or digital outputs/LED drivers with open drain pull-downs that can be pro- SDA (Pin 2): Serial Data Input. This is a bidirectional data grammed to blink. GPIO pins can be programmed to pin which normally has an external pull-up resistor or produce faults due to changes in their logic states, and current source and can be pulled down by the open drain these faults can only be cleared by software or powering device on the LTC1840 0r by external devices. The master the LTC1840 down. All GPlOs default to nonfaulting logic controls SDA during addressing, the writing of data, and inputs upon power-up and their functionality is changed read acknowledgment, while the LTC1840 controls SDA through the serial interface. when data is being read back and during write acknowl- GND (Pin 8): Ground. Connect to analog ground plane. edgment. SDA data is shifted in orouton rising SCL edges. SDA has a logic threshold of lV. . TACHA (Pin 11): Tachometer Input A. This pin is a digital Jtthatis designed to interface to the tachometer output Al (Pin3):Three State Address ProgrammingInput.This fr;op:ittal 3-wire fan. Internal logic counts between rising pin can cause three different logic states internally, de- TACHA edges at serially programmable frequencies of pending upon whether it is pulled to supply, pulled t0 25kHz, 12.5kHz, 6.25kHz or 3.125kHz and the most re- ground,or not connected (NC).Combined with the AO pin, cently completed count is stored in a register accessible this provides for nine different possible two-wire bus through the serial interface. The maximum count is 255 addresses for the LTC1840 (see Table l). and the LTC1840 is prog rammable to produce faults when AO (Pin 4): Three State Address Programming Input. See a count exceeds this number. This pin has CMOS th resh- Al. olds and the default conditions are to count at 3.125kHz FAULT (Pin 5): Fault Indicator Pull-Down Output. This pin and to not produce faults. has an open drain pull-down that is used to signal various TACHB (Pin 12): Tachometer Input B. See TACHA 1840f L7 L,lr19t,V2 )GY