| PARAMETER | SYMBOL | MIN | TYP | MAX | UNITS |
| CLOCK SIGNAL TIMING |
| OSC Clock Period (Typ. 44MHz) | tCYC | 20 | 20 8 | 200 | ns |
| High Period | tH1 | 10 | 10 4 | | |
| Low Period | tL1 | 10 | 10 4 | | |
| EXTERNAL MEMORY READ INTERFACE |
| MOE-Setup Time from RAMCS | tSl | 0 | | | ns |
| MOE_Setup Time from MA (17..0) | tS2 | 0 | | | ns |
| MA (17..1) Hold Time from MOE_ Rising Edge | tH1 | 20 | | | ns |
| RAMCS_ Hold from MOE_ Rising Edge | tH2 | 20 | | | ns |
| MD (15..0) Enable from MOE_ Falling | tE1 | 5 | | | ns |
| MO (15..0) Disable from MOE_ Rising Edge | tD1 | | | 100 | ns |
| EXTERNAL MEMORY WRITE INTERFACE |
| MA (17..0) Setup to MWE_ Falling Edge | tS3 | 0 | O | O | ns |
| RAMCS Setup to MWE | tS4 | 0 | | | ns |
| MA (17..0) Hold from MWE Rising Edge | tH3 | 15 | | | ns |
| RAMCS Hold from MWE_ Rising Edge | tH4 | 15 | | | ns |
| MD (15..0) Setup to MWE_ Rising Edge | tS5 | 40 | | | ns |
| MD (15..0) Hold from MWE Rising Edge | tH5 | 15 | | | ns |
| SYNTHESIZER |
| SYNTHCLK(PKl) Period | tCYC | 83 | | 4,000 | ns |
| | | | | |
