| Pin | Function | Description |
| 1 | RF Input | RF input pin. This pin is internally connected to the bias circuits. An external DC blocking capacitor is required. The value of this capacitor depends on the actual operating frequency. |
| 2 | PD | Power down control voltage. When this pin is at OV, the device will be in power down mode, dissipating minimum DC power. When this pin is at VCC (3V t0 6.5V), the device will be in full power mode delivering maximum gain and output power capability. This pin may also be used to perform some degree of gain control or power control when set to voltages between OV and VCC. It is not optimized for this function so the transfer function is not linear over a wide range as with other devices specifically designed for analog gain control, however, it may be useable for course adjustment or in some closed loop AGC systems. This pin should not, in any circumstance, be higher in voltaae than VCC. This Oin should also have an external bypassing capacitor. |
| 3 | RFIN2 | RF input of the power stage. This pin is internally connected to the bias circuits. An external DC blocking capaator is required. This same capacitor can also be used for interstage matching. Typically this capacitor will be between oin 3 and 4 and have a value of 20 pF at 500 MHz, and 10 pF at 915 MHz. |
| 4 | OUT1 | RF output of the pre-amplifier. Power supply needs to be supplied to this pin through an inductor with a paraUet resistor to avoid oscillations. A parallel capacitor is also needed to tune for parallel resonance at the operating freauencv. This outout is normally connected to pin 3 through a capacitor. |
| 5 | VCC1 | Positive supply for the active bias circuits. This needs to be bypassed with a single capacitor, placed as close as possible to the package. Additional bypassing of lLcF is also recommended, but proximity to the package is not as critical. |
| 6 | RF OUT | Amplifier RF output. This is an unmatched collector output of the final amplifier transistor. It is intemally connecteci to pins 6 and 7. Bias for the final power amplifier output transistor must also be provided through one of these two pins. Typically, pin 6 is connected to a network that provides the DC bias and also creates a second harmonic trap. For 915 MHz operation, this harmonic trap network is simply a single 2 pF capacitor from the pin to ground. This capacitor series resonates with internal bond wires and acts as a trap at two times the operating frequency, effectively shorting out the 2nd harmonic. Shorting out this harmonic serves to increase the amplifiets maximum output power and efficiency, as well as to lower the level of the 2nd harmonic output. Typically, pin 7 is externally connected very close to the package and used as the RF output with a matching network that presents the optimum load impedance to the PA for maximum power and efficiency, as well as providing DC blocking at the outout. |
| 7 | RF OUT | Same as pin 6 |
| 8 | N/C | Not connected. |
| Package Base | Ground | The package base need to be connected directly to the ground plane. Especially at higher frequencies this requires to have vias under the device. |
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