| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact |
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STV92T195 Datasheet Implements two Utopia L2 Slaves providing a solution to bridge Utopia Master devices Compliant with ATM-Forum af-phy-0039.000, June 1995 Single PHY Meets 50MHz performance offering up t0 400Mbps cell rate transfers Single chip solution for improved system integration Support cell level transfer mode Cell and clock rate decoupling with on chip FIFOs Up t0 1.5 KByte of on chip FIFO per data direction Integrated management interface and built-in errored cell discard ATM Cell size programmable via external pins from 16 t0 128 bytes Optional Utopia parity generation/checking enable/disable via external pin Built in JTAG port (IEEE1149 compliant) Simulation model available for system level verification (Contact Quicklogic for details) Solution also available as flexible Soft-IP core, delivered with a full device modelization and verification testbenches STV92T195 Price Two different timing diagrams are shown below. Waveform 1 shows the SCK signal being low when CS makes a high- to-low transition, and Waveform 2 shows the SCK signal being high when CS makes a high-to-low transition. Both waveforms show valid timing diagrams. The setup and hold STV92T195 on stock
The wiper settings are controllable through the I2C compatible digitalinterface, which can also be used to read back the present wiper register control word. The resistance between the wiper and either end point of the fixed resistor varies linearly with respect to the digital code transferred into the RDAC' latch. |
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