ADMap-4  > STV297J-S

suppliers of STV297J-S and PDF data of STV297J-S

Part Numbert Mfg Packt D/C Descriptiont Qty Company/Contact  

STV297J-S Datasheet

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ANALOG SWITCH
Analog-Signal Range VX-, VY-, VZ-, VX, VY, VZ CE OVcc V
vcc = 3V; Ix, IY, lz = 10mA; TA= +250C 8 20
Switch On-Resistance RON VX, VY, VZ = 1.5V CE 25
X-, Y-, Z- Off-Leakage IXJOFF), vcc = 3.6V; Vx_, VY_, Vz_ = 1V, 3V; TA= +250C 1 0 002 1
Current (lxlote 5) IY_(OFF), IZ_(OFF) VX, VY, VZ = 3V, 1V CE -10 10 nA
X, Y, Z Off-Leakage IX(OFF), vcc = 3.6V; VX_, VY_, VZ_ = 1V, 3V; TA= +250C 1 0 002 1
Current (lxlote 6) IY(OFF), IZ(OFF) VX, VY, VZ = 3V, 1V CE -10 10 nA
X, Y, Z On-Leakage IX(ON), vcc = 3.6V; Vx, VY, Vz = 3V, 1V; TA= +250C 1 0 002 1
Current (lxlote 6) IY(ON), IZ(ON) VX-, VY-, VZ- = 3V, 1V, or floating CE -10 10 nA
DIGITAL l/0
Input Voltage High VAH, VBH, VCH, VENABLEH CE 2 0 V
Input Voltage Low VAL, VBL, VCL, VENABLEL CE 0 5 V
Input Current High IAH, IBH, ICH, IENABLEH VA, VB, VC = VENABLE = VCC CE 1 0 0003 1 uA
Input Current Low IAL, IBL, ICL, IENABLEL VA, VB, VC = VENABLE = 0 CE 1 0 0003 1 UA
SWITCH DYNAMIC CHARACTERISTICS
Enable Turn-On Time VX-, VY-, VZ- = 1.5V; RL = 300l ; TA= +250C 9 20
(Note 6) toN CL = 35pF; Figure 3 CE 25 ns
Enable Turn-Off Time VX-, VY-, VZ- = 1.5V; RL = 300l ; TA= +250C 6 15
(Note 6) tOFF CL = 35pF; Figure 3 CE 20 ns
Address Transition VX-, VY-, VZ- = 1.5\//0; RL = 300l ; TA= +250C 9 20
TimeJote 6) tTRANS CL = 35pF; Figure 2 CE 25 ns
Break-Before-Make Time (Klote 6) tBBM VX-, VY-, VZ- = 1.5V; RL = 300 1 ; CL = 35pF TA= +250C 0 2 1 5 ns
Charge Injection (Klote 6) Q c = 1nF, RS = 0, VS = 0, Figure 5 TA= +250C 3 pC
POWER SUPPLY
vcc = 3.6V, TA= +250C 1
Power-Supply Current ICC VA, VB, VC, VENABLE = VCC or 0 CE 10 UA


STV297J-S Price

fSAMPLE=2( JOkHz
= 3.6V
----
VIN=3~
IN=2 7V


STV297J-S on stock
The CMOS shift register and latches allow direct interfacing with micro- processor-based systems. With a 5 V logic supply, serial-data input rates are typically over 5 MHz, with significantly higher speeds obtainable at 12 V. Use with TTL may require appropriate pull-up resistors to ensure an input logic high.

Gate to source charge Qgs VD D =-1 0V, /D =-0.39A -0.04 -0.05 nC
Gate to drain charge qd -0.4 -0.5
Gate charge total Qg VD D =-10V, /D =-0.39A, VGS=O to -4.5V -0.5 -0.62
Gate plateau voltage V(plateau) VD D =-10V, /D =-0.39A -2.2 -2.7 V