| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact |
|
STTNLS373B1 Datasheet The input impedance of Port l, 2, 2 are programmable through the register IOCON. The ALF bit (IOCONO) set all of the Port l, 2, 3 floating when a Power Down mode occurs. The PIHZ, P2HZ, P3HZ bits (IOCONl, IOCON2, IOCON3) set respectively the Ports Pl, P2, P3 in floating state. The IZC (IOCON4) allows to choose input impedance of all ports (Pl, P2, P3). When IZC = 0, T2 and T3 pullup ofl/0 ports are active ; the internalinput impedance is approximately 10 K. When IZC = 1 0nly T2 pull-up is active. The T3 pull-up is turned offby IZC. The internalimpedance is approximately 100 K. STTNLS373B1 Price Implements two Utopia L3 Masters providing a solution to bridge Utopia Slave devices Compliant with ATM-Forum af-phy-0136.000 (Utopia L3) Meets 90 MHz performance offering more than 622 Mbps cell rate transfers Single chip solution for improved system integration Support cell level transfer mode Cell and clock rate decoupling with on chip FIFOs Up t0 1.5 KByte of on chip FIFO per data direction Integrated management interface and built-in errored cell discard ATM Cell size programmable via external pins from 16 t0 128 bytes Optional Utopia parity generation/checking enable/disable via external pin Built in JTAG port (IEEE1149 compliant) Simulation model available for system level verification (Contact Quicklogic for details) Solution also available as flexible Soft-IP core, delivered with a full device modelization and verification testbenches STTNLS373B1 on stock
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
