| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact | |
| STTH1506DI | ST | TO-220 | 05+ | STOCK | 30000 |
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| STTH1506DI | ST | 优势库存 特价出售 | TO-220 | 06+ |
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| STTH1506DI | 12000 |
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| STTH1506DI | New&original/stock | 50 |
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STTH1506DI Datasheet
STTH1506DI Price Data Entry and Control The SP8858is programmed using the serialdatainterface. Data is entered into the chip on the DATA pin and clocked into the internal shift register by the positive going edge of the CLOCK signalwith the ENABLE pin held high.While ENABLE is high, changes to the shift register will not affect the current count cycle. On the falling edge of ENABLE the data held in the shift register is transferred to one of the three buffers (F1, F2 0r reference). Fig. 4 shows the timing requirements for these three signals. The 2 LSBs ofthe 24-bitshift register, C1 and C2,determine which of the three buffers is loaded with the data held in the STTH1506DI on stock 222mW = (VIN - 3.OV) 80mA + VIN X 3mA 222mW = (80mA x VIN +3mA x VIN) - 240mW 462mW = 83mA x VIN VIN = 5.57V max. Therefore, a 3.OV application at 80mA of output current can accept a maximum input voltage of 5.6V in an SC-70-5 package. For a full discussion of heat sinking and thermal effects on voltage regulators, refer to Regulator Thermals section of Micrel's Designing with Low-Dropout Voltage Regu- lators handbook.
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