STTDA7294 Datasheet| Electrical Specifications: Unless otherwise specified, VIN = VR + 1V, IL = 100 IJA, COUT = 3.3 pF, SHDN > VIH, TA = +250C. BOLDFACE type specifications apply for junction temperature of -400C to +1250C. | | Parameters | Sym | Min | Typ | Max | Units | Conditions | | Input Operating Voltage | VIN | 2.7 | | 6.0 | V | Note 1 | | Maximum Output | oOUTMAX | 50 | | | mA | TC2014 | | Current | 100 | | | TC2015 | | 150 | | | TC2185 | | Output Voltage | VOUT | VR- 2.0% | VR±0.4% | VR+ 2.0% | V | Note 2 | | VOUT Temperature | TCVOUT | | 20 | | ppm/oC | Note 3 | | Coefficient | | 40 | | | Line Regulation | AVOUT/AVIN | | O05 | 0.5 | % | (VR + 1V) .< VIN < 6V | | Load Regulation | AVOUTNOUT | ·1.0 | 0 33 | +1.0 | % | TC2014;TC2015: 11 = 0.1 rriA to IOUTMAX | | (Note 4) | ·2.0 | 0 43 | +2.0 | TC2185: 11 = 0.1 mA to IOUTMAX Note 4 | | Dropout Voltage | VIN - VOUT | | 2 | | mV | Note 5 11 = 100 pA | | | 45 | 70 | l= 50 mA | | | 90 | 140 | TC2015; TC2185 11= 100 mA | | | 140 | 210 | TC2185 11 = 150 mA | | Supply Current | IIN | | 55 | 80 | pA | SHDN = VIH,IL=O | | Shutdown Supply Current | IINSD | | 0 05 | 0 5 | UA | SHDN= OV | | | | | | | |
STTDA7294 Price| Symbol | Parameter | Test Conditions | Min | Typ. | Max | Unit | | td(off) tf | Turn-o Delay Time Fall Time | VDD = 30 V ID = 1 A RG = 4.7 [ , VGS = 4.5 V (Resistive Load, Figure l) | | 42 15 | | ns ns | | | | | | | |
STTDA7294 on stock| Pin | Input/Output | Name | Description | Interface | | VDD | Power | Power supply & | for logical circuit (+3V, +5V) | Power supply | | VSS (GND) | LCD bias pin | OV (GND) | | V2V3V5 | Bias voltage level for LCD driving | | S1 - S40 | Output | Segment output | Segment signal output for LCD driving | LCD | | C1 - C16 | Input | Common output | Common signal output for LCD driving | LCD | | EXTCLK | Input | External clock Input | When using external clock, used as clock input pin. When using internal oscillator, connect to VDD or VSS. | External clock | | EXT INT | Input | External/internal oscillator clock select | When EXT_INT = "High", external clock is used. When "Low", internal oscillator is used. | VDDNSS | | RS | Input | Register select | Used as register selection input. When RS = "High", Data register is selected. When RS = "Low", Instruction register is selected. | MPU | | R/W | Input | Read/write | Used as read/write selection input. When R/W = "High", read operation. When R/W = "Low", write operation. | | E | Input | Read/write enable | Used as read/write enable signal. | | DBO-DB3 | Input/Output | Data bus O -7 | When 8-bit bus mode, used as low order bi-directional data bus. During 4-bit bus mode open these pins. | | DB4-DB7 | When 8-bit bus mode, used as high order bi- directional data bus. In case of 4-bit bus mode, used as both high and low order. DB7 is used for busy flag output during read instruction operation. | | RESETB | Input | Reset | If it is necessary to initialize the system by hardware, force "Low", level signal to this terminal about l.2ms. | | TEST | Output | Test pin | Internal oscillator test pin. Open this pin. | Open | | | | | |
The command operation "Set PWM Duty Cycle" is used to configure the output duty cycle of the device. The DS1050 has a 5-bit resolution and is capable of setting the duty cycle output from 0% up t0 96.88% in steps of 3.125%. A binary value of (OOOOOB) sets the duty cycle output at 0% while a binary value of (11111B) sets the duty cycle output at 96.88%.
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