STT181 Datasheet| min | typ. | max | | gfs lC =IC90;VCE=10V, 30 Pulse test, t i 300 us, duty cycle i 2 % | 55 | S | | C. C VCE = 25 V, VGE = 0 V, f =1 MHz oes C C res | 4000 290 100 | pF pF pF | | Qn g Q le = IC90, VGE = 15 V, VCE = 0.5 VCES ge Qnr ge | 200 35 80 | nC nC nC | | td(on, Inductive load. Tj = 250C t . Ie = IC90, VGE = 15 V, L = 100 uH, r, V.E = 0.8 VCES, RG = Roff = 2.7 Q td(off, Remarks: Switching times may increase tf, for VCE (Clamp 0.8 . VCES, higher Tj or Eoff increased RG | 50 30 300 360 8 | ns ns 600 ns 570 ns 15 mJ | | td(on, Inductive load. Tj = 1250C t. ri lC = IC90, VGE = 15 V, L = 100 vH c E on VCE = 0.8 VCES, RG = Roff = 2.7 Q td(off, Remarks: Switching times may increase tf, for VCE (Clamp 0.8 . VCES, higher Tj or increased RG Eoff | 50 30 3 650 550 17 | ns ns mJ ns ns mJ | | RthjC RthCK | 0.05 | 0.50 K/W K/W | | | |
STT181 Price| Parameters | Speclflcatlon limit | UnIts | | | +25 | -55 to +85 | C | | Frequency r=rnge | so - 500 | MHz | | Small signal gain | 32O±0.8 | | dB | | | | +0.5/-1.0 | dB Max | | Gain flatness | 1 0 | I5 | dB Max p-p | | | 33 | 33 | dB Min | | VSWR Input Output | I5:1 1 .5:I | 1.5:1 I .5:1 | Max Max | | I dB compression | +15 | +14 | dBm Min | | Output intercept point 3rd Order 2nd Order | +z5 35 | 21 +30 | dBm Min dBm Min | | Noise figure | 3.5 | 4 0 | dB Max | | DC power@ 15 Vdc + l% | 70 | 70 | mA Max | | Gain vs. Vdc | O40 | | dB/Volt Max | | Housing | TO-B LP (see page P-13 far details) | | | | |
STT181 on stock The K9K1208UOA has addresses multiplexed int0 8 l/O's. This scheme dramatically reduces pin counts and allows systems upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through l/O's by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the l/0 pins. All commands require one bus cycle except for Block Erase command which requires two cycles: one cycle for erase-setup and another for erase-execution after block address loading. The 64M byte physical space requires 26 addresses, thereby requiring four cycles for byte-level addressing: col- umn address, low row address and high row address, in that order. Page Read and Page Program need the same four address cycles following the required command input. In Block Erase operation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into the command register. Table l defines the specific commands of the K9K1208UOA. | Section | Overview 'his section covers the hardware specifIcations of the IM2000S. Covered are: I Mechanical SpecifIcations I Electrical SpecifIcations I Pin Description | | |
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