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This design assumes that the PGA Am29030 proces- sor's Scalable Clocking W feature is used, resulting in a 32-MHz processor with a 16-MHz external memory and PCI bus interface. The worst-case timing in this design then occu rs in the memory system around a single-cycle read at 16 MHz. The delay must be set at 20 ns for the CAS pulse generation while 12 ns is the best time of a MACH220 device for the combinatorial delay, making CAS fall at 32 ns into the cycle. CAS access time is 20 ns. A set up of 9 ns makes an access time of61 ns for a 62.5-ns cycle at 16 MHz. If additional setup or CAS ac- cess time is needed, then the RAS/CAS decode can be accomplished in a separate, faster decode PAL device. The DELAY signal from the delay line can be used in this PAL device, with the other state lines going to the faster decode PAL device. Additionally, faster address multi- plexers can be used,such as 74F orAS parts, instead of the 74LS157s. This reduces the delay from 12 ns t0 6 ns and decreases the delay line requirement t0 15 ns, gain- ing an additional 5 ns on CAS access. Use ofthese fast- er 74F/AS157s then requires 33-ohm series dampening resistors before the DRAMs.