| Pin | Function | Description | Interface Schematic |
| 1 | RF IN | RF input. Input is matched t0 50Q and DC block is provided internally. | VCC1 p |
| 2 | NC | No connect. Recommend connecting to ground. | |
| 3 | BIASIGND | Ground for first stage bias circuit. For best performance, keep traces physically short and connect immediately to ground plane. | See pin 4 |
| 4 | VREG1 | First stage input bias. This pin requires a regulated supply to maintain | s | |
| nominal bias current. | o o BIAS BIAS GNDl GND2 |
| 5 | VREG2 | Second stage input bias. This pin requires a regulated supply to main- tain nominal bias current. Usually connected to VREGl. | See pin 4 |
| 6 | BIAS2GND | Ground for second stage bias circuit. For best performance, connect to ground with a choke inductor. | See pin 4 |
| 7 | PWR SEN | Provides an output voltage proportional to output RF level. | |
| 8 | RF OUT | RF output. Output is matched t0 50Q and DC block is provided inter- nally. | /RFOUT |
| 9 | RF OUT | Same as pin 8 | See pin 8 |
| 10 | VCC2 | Second stage output bias. Supply should be connected through a choke inductor sized appropriately to handle the output bias current. | See pin 8 |
| 11 | VCC2 | Same as pin 10. | See pin 8 |
| 12 | VCC1 | First stage output bias. This pin is sensitive to bypass capacitors placed close to it. Place an RF short approximately 200mils from this pin before any other supply connections. | See pin 1 |
| Pkg Base | GND | Ground connection. The backside of the package should be connected to the ground plane through a short path (i.e., vias under the device will be required). | |
| | | | |
The second monitoring function is push-button reset control. The DS1673 provides for a pushbutton switch to be connected to the RST output pin. When the DS1673 is not in a reset cycle, it continuously monitors the RST signal for a low going edge. If an edge is detected, the DS1673 will debounce the switch by pulling the RST line low. After the internal 250 ms timer has expired, the DS1673 will continue to monitor the RST line. If the line is still low, the DS1673 will continue to monitor the line looking for a rising edge. Upon detecting release, the DS1673 will force the RST line low and hold it low for 250 ms.
| | | | | Ta=25 | Ta=-4085 | |
| CHARACTERISTIC | SYMBOL | TEST CONDITION | Vcc | MIN. | TYP | MAX. | MIN. | MAX. | UNIT |
| Output Transition Time | tTLH tTHL | | 2.0 4.5 6.0 | | 25 7 6 | 75 15 13 | | 95 19 16 | ns |
| Propagation Delay Time | tpLH tpHL | | 2.0 4.5 6.0 | | 27 8 7 | 75 15 13 | | 95 19 16 | ns |
| Input Capacitance | CIN | | | 5 | 10 | | 10 | |
| Power Dissipation Capacitance | CPD | (Note l) | | 2l | | | | pF |
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