| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact |
STR45111 T Datasheet
STR45111 T Price . E1-Related Telecommunications Specifications . ITUT G.703 Physical/Electrical Characteristics of G.703 Hierarchical Digital Interfaces * ITUT G.736 Characteristics of Synchronous Digital Multiplex Equipment operating at 2048 Kbit/s * ITUT G.742 Second Order Digital Multiplex Equipment Operating at 8448 Kbit/s . ITUT G.772 Protected monitoring points provided on digital transmission systems * ITUT G.775 Loss of signal (LOS) and alarm indication signal (AIS) defect detection and clearance criteria . ETSI 300 166 Physical and electrical characteristics of hierarchical digital interfaces for equipment using the 2,048 kbit/s-based plesiosynchronous or synchronous digital hierarchies . ETSI 300 233 Integrated Services Digital Network (ISDN) * G.736 Characteristics of a synchronous digital multiplex equipment operating at 2048 kbit/s * G.823 The control of jitter and wander within digital networks which are based on the 2048 kbit/s hierarchy . Pub 62411 High Capacity Terrestrial Digital Service STR45111 T on stock
Auto Refresh is used during normal operation of the GDDR3 SDRAM and is analogous to /CAS-BEFORE-/RAS (CBR) REFRESH in FPM/EDO DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits a "Don't Care" during an Auto Refresh command. The 256Mb(x32) DDR2(x32) requires Auto Refresh cycles at an average interval of 7.8us (maximum). , meaning that the maxi- mum absolute interval between any Auto Refresh command and the next Auto Refresh command is 9 x 7.8us(70.2us). This maximum absolute intervalis to allow GDDR3(x32) SDRAM output drivers and internal terminators to automatically recalibrate compensating for voltage and temperature changes. |
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