STR30128 Datasheet| | | TL321C | TL3211 | | | PARAMETER | TEST CONDITIONSt | MIN TYP MAX | MIN TYP MAX | UNIT | | | VIC = VICR min, | 25YC | 2 7 | 2 5 | | | VIO Input offset voltage | VCC = 5 V t0 30 V, vo = 1.4 V, RS = 50 kl | Full range | 9 | 7 | mV | | | | 25YC | 5 50 | 3 30 | | | 110 Input offset current | VO= 1.4 V | Full range | 150 | 100 | nA | | | | 25YC | -45 -250 | -45 -150 | | | IIB Input bias current | VO= 1.4 V | Full range | -500 | -300 | nA | | ,. Common-mode input voltage | | 25YC | 0 to VCC -1.5 | 0 to VCC -1.5 | V | | VICR range | VCC =5 V t0 30 V | Full range | 0 to VCC -1.5 | 0 to VCC -1.5 | | | vcc = 30 V, RL=2k[ | Full range | 26 | 26 | V | | VOH High-Ievel output voltage | vcc = 30 V, RL >10 kl | Full range | 27 28 | 27 28 | | RL>2k | 25YC | 3.5 | 3.5 | | VOL Low-Ievel output voltage | RL >10 kl | Full range | 5 20 | 5 20 | mV | | | vcc = 15 V, | 25YC | 25 100 | 50 100 | | | AVDLarge-signalI | VO =1 V t0 11 V, RL=2kj | Full range | 15 | 25 | V/mV | | CMRR Common-mode rejection ratio | VIC = VICR min, RS = 50 kl | 25YC | 65 85 | 70 85 | dB | | age rejection ratio kSVR S(qVp~9XJtlOg)e o) | vcc = 5 V t0 30 V, RS = 50 kl | 25YC | 65 100 | 65 100 | dB | | | | vcc = 15 V. | 25YC | -20 -40 | -25 -40 | | | Source | VID = 1 V, VO =0 | Full range | -10 -20 | -10 -20 | | [0 0utput current | | vcc = 15 V. | 25YC | 10 20 | 10 20 | mA | | Sink | VID = -1 V, VO =15 V | Full range | 5 8 | 5 8 | | | VID = -1 V, vo = 200 V | 25YC | 12 50 | 12 50 | | | | No load, vo = 15 V, VCC = 30 V | Full range | 2 | 2 | | | ICC Supply current | No load, vo = 2.5 V, vcc = 5 V | Full range | 1 | 0 4 1 | mA | | | | | | | |
STR30128 Price| Items | Symbols | Test Conditions | Min | Typ | Max | Units | | | Rtr,ri_c) | IGBT | | | 0.16 | | | Thermal Resistance | Rtr,ri_c) | Diode | | | 0.35 | oc/w | | Rtr,cc_f) | With Thermal Compound | | 0.025 | | | | | | | | |
STR30128 on stock| Analog Signals | Pin | IO | Description | | AIN1 | 17 | I | Input to Converter #1 | | AIN2 | 14 | I | Input to Converter #2 | | AIN3 | 18 | I | Input to Converter #3 | | AIN4 | 15 | I | Input to Converter #4 | | AIN5 | 19 | I | Input to Converter5 | | AIN6 | 16 | I | Input to Converter #6 | | VCIN | 10 | I | Input to Voltage Monitoring Block | | | | |
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driv- en High. A Stop condition terminates communica- tion between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Stand-by mode. A Stop condition at the end of a Write command triggers the internal EE- PROM Write cycle.
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