| Clock Cycle Number | Clock Cycle Count | Field | LADO- LAD3 | Memory l0 | Description |
| 1 | 1 | START | OOOOb | l | On the rising edge of CLK with LFRAME Low, the contents of LADO-LAD3 must be OOOOb to indicate the start of a LPC cycle. |
| 2 | 1 | CYCTY PE+ DIR | OllXb | l | Indicates the type of cycle. Bits 3:2 must be Olb. Bit 1 indicates the direction of transfer: 1b for write. Bit o is don't care (X). |
| 3-10 | 8 | ADDR | XXXX | l | A 32-bit address phase is transferred starting with the most significant nibble first. A26-A31 must be set t0 1. A22 = 1 for Array, A22 = 0 for registers access. For A21, A23-A25 values, refers to Table 2. |
| 11-12 | 2 | DATA | XXXX | l | Data transfer is two cycles, starting with the least significant nibble. |
| 1 3 | 1 | TAR | 1111b | l | The host drives LADO-LAD3 t0 1111b to indicate a turnaround cycle. |
| 14 | 1 | TAR | 1111b (float) | O | The LPC Flash Memory takes control of LADO-LAD3 during this cycle. |
| 1 5 | 1 | SYNC | OOOOb | O | The LPC Flash Memory drives LADO-LAD3 to OOOOb, indicating it has received data or a command. |
| 1 6 | 1 | TAR | 1111b | O | The LPC Flash Memory drives LADO-LAD3 t0 1111b, indicating a turnaround cycle. |
| 1 7 | 1 | TAR | 1111b (float) | N/A | The LPC Flash Memory floats its outputs and the host takes control of LADO-LAD3. |
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