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STR-NLH-34 Datasheet

The Soft-Start will not take place, and the relative pin is internally shorted to GND, if both VCC and OCSET pins are not above their own turn-on thresholds. During normal operation, if any under-voltage is detected on one of the two supplies, the SS pin is internally shorted to GND and so the SS capacitor is rapidly discharged.
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I I AIN = 9.6MHz
AIN = -1.OdBFS SNR = 66.05dB
THD = 74.28dB SFDR = 75.32dBFS






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STR-NLH-34 on stock

SYMBOL	PARAMETER	CONDITIONS		MIN TYP MAX	UNITS
lo	Ouiescent Current	Switch Off	q	300	cCA
VIN	Input Voltage	Step-Up Mode	q	1.15 12.6 1.0 12.6	V V
VIN	Input Voltage	Step-Down Mode	q	30	V
	Comparator Trip Point Voltage	LT1110 (Note l)	q	210 220 230	mV
VOUT	Output Sense Voltage	LT1110-5 (Note 2)	q	4.75 5.00 5.25	V
VOUT	Output Sense Voltage	LT1110-12 (Note 2)	q	11.4 12.00 12.6	V
	Comparator Hysteresis	LT1110	q	4 8	mV
	Output Hysteresis	LT1110-5	q	90 180	mV
	Output Hysteresis	LT1110-12	q	200 400	mV
fosc	Oscillator Frequency		q	52 70 90	kHz
DC	Duty Cycle	Full Load (VFB < VREF)	q	62 69 78	%
tON	Switch ON Time		q	7.5 10 12.5
IFB	Feedback Pin Bias Current	LT1110, VFB = OV	q	70 150	nA
ISET	Set Pin Bias Current	VSET= VREF	q	100 300	nA
VAO	AO Output Low	IAO = -300ccA, VSET = 150mV	q	0.15 0.4	V
	Reference Line Regulation	1.OV " VIN " 1.5V	q	0.35 1.0	%/V
	Reference Line Regulation	1.5V " VIN " 12V	q	0.05 0.1	%N

When the SPI is operated in slave mode, the SPI clock must be configured to a baud rate as close to the master's baud rate as possible. If the baud rate is too slow, the enable signal wil not be generated in time to keep the master from sending additional data. If the baud rate is too fast, the slave will capture the data before the last bit is shifted in.

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