STR-D6802 Datasheet| | | | Limits | | | Symbol | Parameter | Test conditions | Min | Typ | Max | Unit | | V (BR) DSS | Drain-source breakdown voltage | ID = ImA, VGs = OV | 700 | | | v | | V (BR) GSS | Gate-source breakdown voltage | IGS = +100ffA, VDS = OV | ±30 | | | v | | IGSS | Gate-source leakage current | VGS = +25V, VDS = OV | | | ±10 | | | IDSS | Drain-source leakage current | VDS = 700V, VGS = OV | | | 1 | mA | | VGS (th) | Gate-source threshold voltage | ID = 1ffiA, VDS = 10V | 2 | 3 | 4 | v | | rDS (ON) | Drain-source on-state resistance | ID = 2A, VGS = 10V | | 2.0 | 2 6 | | | VDS (ON) | Drain-source on-state voltage | ID = 2A, VGS = 10V | | 4 0 | 5 2 | v | | yfs | Forward transfer admittance | ID = 2A, VDS = 10V | 2 5 | 4.2 | | S | | Ciss | Input capacitance | | | 770 | | pF | | Coss | Output capacitance | VDS=25V,VGS=Oy f=1MHz | | 88 | | pF | | Crss | Reverse transfer capacitance | | 16 | | pF | | td (on) | Turn-on delay time | | | 15 | | ns | | tr | Rise time | VDD = 200y ID = 2A, VGS = 10V, | | 18 | | ns | | td (off) | Turn-off delay time | RGEN = RGS = sol | | 90 | | ns | | tf | Fall time | | 25 | | ns | | VSD | Source-drain voltage | Is = 2A, VGS = OV | | 1.0 | 1 5 | v | | Rth (ch-c) | rhermal resistance | Channel to case | | | 1 25 | IC/W | | | | | | | |
STR-D6802 Price The ZL30109 is a DSl/E1 System Synchronizer providing timing (clock) and synchronization (frame) signals to interface circuits for DSl and El Primary Rate Digital Transmission links and OC-3/STM-1 links, as well as a 19.44 MHz output for SDH line card applications. Figure l is a functional block diagram which is described in the following sections. STR-D6802 on stock| VCC | CE | CE2 | OE | WE | MODE | DQ | POWER | | | VIH | X | X | X | DESELECT | HIGH Z | STANDBY | | 5 VOLTS | X | VIL | X | X | DESELECT | HIGH Z | STANDBY | | VIL | VIH | X | VIL | WRITE | DATA IN | ACTIVE | | ±10% | VIL | VIH | VIL | VIH | READ | DATA OUT | ACTIVE | | VIL | VIH | VIH | VIH | READ | HIGH Z | ACTIVE | | <4.5 VOLTS >VBAT | x | x | x | x | DESELECT | HIGH Z | CMOS STANDBY | | <VBAT | x | x | x | x | DESELECT | HIGH Z | DATA RETENTION MODE | | | | | | | | |
| Symbol | Parameter | Test Conditions | Min | Typ. | Max | Unit | | td(on) tr | Turn-on Time Rise Time | VDD = 25 V ID = 6 A RG = so I VGS = 10 V (see test circuit figure) | | 40 80 | 60 120 | ns ns | | (di/dt)on | Turn-on Current Slope | VDD = 40 V ID = 12 A RG = so I VGS = 10 V (see test circuit figure) | | 210 | | Als | | Qg Qgs Qgd | Total Gate Charge Gate-Source Charge Gate-Drain Charge | VDD = 40 V ID = 12 A VGS = 10 V | | 15 6 5 | 25 | nC nC nC | | | | | | | |
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