| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact |
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STPS3545CP Datasheet The internal SPT774 12-bit CDAC is sequenced by the SAR starting from the MSB to the LSB at the beginning of the conve rsion cycle to provide an output voltage from the CDAC thatis equal to theinputsignal voltage (which is divided bythe input voltage divider network). The comparator determines whether the addition of each successively-weighted bit volt- age causes the CDAC output voltage summation to be greater or less than the input voltage; if the sum is less, the bit is left on; if more, the bit is turned o. After testing all the bits, the SAR contains a 12-bit binary code which accurately represents the input signal to within +1/2 LSB. STPS3545CP Price The window comparator stage generates two serial data streams, one having logic l states corresponding to ARJNC "High" states (OUTA), and the other having logic l states corresponding to ARINC "Low" states (OUTB). An ARJNC "Null" state at the inputs forces both outputs to logic 0. Thus, the ARJNC clock signal is recovered by applying a NOR function to OUTA and OUTB. STPS3545CP on stock FEATURES * Micro package. ~ High gain bandwidth product. fT = 600 MHz TYP. . Low output capacitance. Cab = 1.0 pF TYP. ABSOLUTE MAXIMUM RATfNGS (Ta = 25 aC) Maximum Voltages and Current Collector to Base Voltage VCB0 30 . Collector to Emitter Voltage VCE0 20 Emitter to Base Voltage VEB0 4.0 Collector Current lC 20 Maximum Power Dissipation Total Power Dissipation PT 150 Maximum Temperatures Storage Temperature Tstg - 55 to +125 Junaion Temperature Tj 125
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