STP4NC60Z Datasheet| PARAMETER | RATING | UNIT | | Core Supply Voltage to Vss | -0.5 t0 4.6 | V | | I/O Supply Voltage to Vss | -0t0 4.6 | V | | Input/Output to Vsso Potential | Vsso -0.5 to VDDQ +0.5 | V | | Allowable Power Dissipation | 1.0 | W | | Storage Temperature | -65 t0 150 | oC | | Operating Temperature | O to +70 | oC | | | |
STP4NC60Z Price| PARAMETER | CONDITIONS | MIN TYP MAX | UNITS | | Resolution (No Missing Codes) | 0.1 .< VREF i VCC, -FS i VIN < +FS (Note 5) | @ | 1 6 | Bits | | Integral Nonlinearity | 5V .< VCC .< 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6) 2.7V .< Vcc .< 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6) | @ | 2 1 0 1 | ppm of VREF | | Offset Error | 2.5V .< VREF < VCC, GND < IN+ = IN- .< Vcc (Note 14) | @ | 0.5 2 | mV | | Offset Error Drift | 2.5V .< VREF iVCC, GND < IN+ = IN-i Vcc | | 100 | nV/oC | | Positive Full-Scale Error | 2.5V .< VREF < VCC, IN+ = 0.75VREF, IN- = 0.25VREF | @ | 25 | ppm of VREF | | Positive Full-Scale Error Drift | 2.5V .< VREF < VCC, IN+ = 0.75VREF, IN- = 0.25VREF | | 0.1 | ppm ol VREF/oC | | Negative Full-Scale Error | 2.5V .< VREF < VCC, IN+ = 0.75VREF, IN- = 0.25VREF | @ | 25 | ppm of VREF | | Negative Full-Scale Error Drift | 2.5V .< VREF < VCC, IN+ = 0.75VREF, IN- = 0.25VREF | | 0.1 | ppm ol VREF/oC | | Output Noise | 5V i VCC .< 5.5V, VREF = 5V, GND i IN- = IN+ < Vcc (Note 13) | | 0.84 | VVRMS | | Programmable Gain | (Note 15) | @ | 1 1 28 | | | | | | |
STP4NC60Z on stock| Parameter | Description | Conditions | Min | Typ. | Max | Unit | | ICLKFR | Input Clock Frequency Range | Non-crystal, 3.OV Pk-Pk ext. source | 25 | | 200 | MHz | | tRISE(a) | Clock Rise Time | SSCLKla or SSCLKlb, Freq = 100 MHz | 1.0 | 1.3 | 1.6 | ns | | tFALL(a) | Clock Fall Time | SSCLKla or SSCLKlb, Freq = 100 MHz | 1.0 | 1.3 | 1.6 | ns | | 'RlSE(a+b) | Clock Rise Time | SSCLKl(a+b), CL = 33 pF, 100 MHz | 1.2 | 1.5 | 1.8 | ns | | tFALL(a+b) | Clock Fall Time | SSCLKl(a+b), CL = 33 pF, 100 MHz | 1.2 | 1.5 | 1.8 | ns | | oRlSE(a+b) | Clock Rise Time | SSCLKl(a+b), CL = 33 pF, 200 MHz | 1.1 | 1.4 | 1.7 | ns | | tFALL(a+b) | Clock Fall Time | SSCLKl(a+b), CL = 33 pF, 200 MHz | 1.1 | 1.4 | 1.7 | ns | | oRlSE(REF) | Clock Rise Time | REFOUT, Pin 3, CL = 15 pF, 50 MHz | 1.0 | 1.3 | 1.6 | ns | | oFALL(REF) | Clock Fall Time | REFOUT, Pin 3, CL = 15 pF, 50 MHz | 1.0 | 1.3 | 1.6 | ns | | DTYin | Input Clock Duty Cycle | XIN/CLK (Pin) | 30 | 50 | 70 | % | | DTYout | Output Clock Duty Cycle | SSCLKla/b (Pin 8 and 9) | 45 | 50 | 55 | % | | CCJ1 | Cycle-to-Cycle Jitter | F = 100 MHz, SSCLKla/b CL = 33 pF | | 300 | 400 | ps | | CCJ2 | Cycle-to-Cycle Jitter | F = 200 MHz, SSCLKla/b CL = 33 pF | | 500 | 600 | ps | | REFOUT | Refout Frequency Range | CL= 15 pF | 25 | | 108 | MHz | | | | | | | |
| | '__ ~.u - +0.05 . 2.0 A | +0.05 n+01._1.55 d | | | __n | UP | | | | | 1.75 / r | | r | | | | | | -0.1 3.5 | l l | L l l | | | | | 8. M×[- .-i | l | l l | | -l- | | | | | l N l l ___ _ ___ | | l ll LU | | l | | l | | | | | | | | | 7±0.05 1.0 | | -v - +o. | O | | | | | | | | | | | |
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