| Pin Name | Pin Type | Description | Number | Share Pin | Reset Value | Circuit Type |
| PO.O PO.1 P0.2 P0.3 | l I/O I/O l | 4-bit input port. 1-bit and 4-bit read and test are possible. 4-bit pull-up resistors are software assignable. | 20 21 22 23 | INT4 SCK SO SI | Input | A-1 D* D* A-1 |
| P1.0 P1 .1 P1.2 P1.3 | l | 4-bit input port. 1-bit and 4-bit read and test are possible. 4-bit pull-up resistors are software assignable. | 24 25 26 27 | INTO INT1 INT2 TCLO | Input | A-1 |
| P2.0 P2.1 P2.2 P2.3 | I/O | 4-bit l/0 port. 1-bit and 4-bit read/write and test are possible. 4-bit pull-up resistors are software assignable. | 28 29 30 31 | TCLOO CLO BUZ | Input | D |
| P3.0 P3.1 P3.2 P3.3 | I/O | 4-bit l/0 port. 1-bit and 4-bit read/write and test are possible. Each individual pin can be specified as input or output. 4-bit pull-up resistors are software assignable. | 32 33 34 35 | LCDCK LCDSY | Input | D |
| P4.0- P4.3 P5.0- P5.3 | I/O | 4-bit l/0 ports. N-channel open-drain output up t0 5 V. 1-, 4-, and 8-bit read/write and test are possible. Ports 4 and 5 can be paired to support 8-bit data transfer. 4-bit pull-up resistors are software assignable. | 36-43 | | Input | E |
| P6.0- P6.3 P7.0- P7.3 | I/O | 4-bit l/0 ports. Port 6 pins are individually software configurable as input or output. 1-bit and 4-bit read/write and test are possible. 4-bit pull-up resistors are software assignable. Ports 6 and 7 can be paired to enable 8-bit data transfer. | 44-51 | KSO-KS3 KS4-KS7 | Input | D* |
| P8.0- P8.7 | O | Output port for l-bit data (for use as CMOS driver only) | 59-52 | SEG24- SEG31 | Output | H-16 |
| SEGO- SEG23 | O | LCD segment signal output | 3-1 80-60 | | Output | H-15 |
| SEG24- SEG31 | O | LCD segment signal output | 59-52 | P8O-P8.7 | Output | H-16 |
| COMO- COM3 | O | LCD common signal output | 4-7 | | Output | H-15 |
| VLCO-VLC2 | | LCD power supply. Voltage dividing resistors are assignable by mask option | 9-11 | SCLK SDAT | | |
| BIAS | | LCD power control | 8 | | | |
| LCDCK | I/O | LCD clock output for display expansion | 32 | P3O | Input | D |
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G7 are Hi-Z input only pins, any attempt by the user to con- figure them as outputs by writing a one to the configuration register will be disregarded. Reading the G6 and G7 configu- ration bits will return zeroes. Note that the chip will be placed in the Halt mode by writing a "1" to the G7 data bit. Six pins of Port G have alternate features: GO INTR (an external interrupt) G3 Tl0 (timer/counter input/output) G4 SO (MICROWIRE serial data output) G5 SK (MICROWIRE clock l/0) G6 Sl (MICROWIRE serial data input) G7 CKO crystal oscillator output (selected by mask option) or HALT restart input/general purpose input (if clock op- tion is R/C- or external clock) Pins Gl and G2 currently do not have any alternate func- tions. The selection of alternate Port G functions are done through registers PSW [OOEF] to enable external interrupt and CNTRL [OOEE] to select Tlo and MICROWIRE operations.
. For purposes of emulation and development support only, a special 180 PGA version is supported. This version adds back the FC2-0, A , FRZ, and A~E~ signals to non multiplexed pins. In the TQFP package when operating in PCMCIA mode, these signals are not available. The FC2-0 pins allow bus cycles to be distinguished between program and data accesses, interrupt cycles, etc. The ~A~, FRZ, and A~E~ pins are provided so that emulation vendors can quickly retrofit their existing MC68302 emulator designs to support the MC68PM302.
