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STN3NF06L. Datasheet

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STN3NF06L. Price
With some optional external components the application circuit can be designed to signal a display when the battery has decayed below a predetermined level, or designed to signal a display at one level and then shut itself off after the battery decays to a second level. See the applications section for these and other unique circuits.
STN3NF06L. on stock

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Phase Adjust The internal clock is aligned to the center of the data eye. For specific applications this sampling position can be shifted using the PHADJ inputs to optimize BER performance. The PHADJ inputs operate with differen- tial input voltages up to +1.5V. A simple resistor-divider with a bypass capacitor is sufficient to set these levels. When the PHADJ inputs are not used, they should be tied directly to VCc.