| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact |
STMM9814-OC-026 Datasheet
STMM9814-OC-026 Price
STMM9814-OC-026 on stock When the oscillator's internal logic circuitry detects a synchronizing signal on the MODE/SYNC pin, the internal oscillator ramp is terminated early and the slope compen- sation is increased by approximately 30%. As a result, in applications requiring synch ronization,itis recommended that the nominal operating frequency of the lC be pro- grammed to be about 75% ofthe external clockfrequency. Attempting to synchronize to too high an external fre- quency (above l.3fo) can result in inadequate slope com- pensation and possible subharmonic oscillation (or jitter). JEDEC standard l.8V + O.1V Power Supply VDDQ = 1.8V + O.1V 200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/pin, 333MHz fCK for 667Mb/sec/pin 4 Banks Posted CAS Programmable ~AS Latency: 3, 4, 5 Programmable Additive Latency: 0, 1 , 2 , 3 and 4 Write Latency(WL) = Read Latency(RL) -1 Burst Length: 4 , 8(lnterleave/nibble sequential) Programmable Sequential/lnterleave Burst Mode Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature) Off-Chip Driver(OCD) Impedance Adjustment On Die Termination Average Refresh Period 7.8us at lower than a TCASE 850C, 3.9us at 850C < TCASE 95 0C - support High Temperature Self-Refresh rate enable feature Package: 60ball FBGA - 32Mx8 All of Lead-free products are compliant for RoHS |
