| Pin Description |
| | SYMBOL | PIN NUMBER | TYPE | DESCRIPTION | |
| Vcc | 31 | | Vcc: is the +5V power supply pin. A O.lffF capacitor between pins 31 and 20 is recommended for decoupling. |
| GND | 20 | | Ground |
| CLK | 12 | I | CLOCK INPUT: The Clock Input is used to generate the timing signals which control 82C37A operations. This input may be driven from DC t0 12.5MHz for the 82C37A-12, from DC t0 8MHz for the 82C37A, or from DC t0 5MHz for the 82C37A-5. The Clock may be stopped in either state for standby operation. |
| CS | 11 | I | CHIP SELECT: Chip Select is an active low input used to enable the controller onto the data bus for CPU communications. |
| RESET | 13 | I | RESET: This is an active high input which clears the Command, Status, Request, and Temporary registers, the First/Last Flip-Flop, and the mode register counter. The Mask register is set to ignore requests. Following a Reset, the controller is in an idle cycle. |
| READY | 6 | I | READY: This signal can be used to extend the memory read and write pulses from the 82C37A to accommodate slow memories or l/0 devices. READY must not make transitions during its specified set-up and hold times. See Figure 12 for timing. READY is ignored in verify transfer mode. |
| HLDA | 7 | I | HOLD ACKNOWLEDGE: The active high Hold Acknowledge from the CPU indicates that it has relinquished control of the system busses. HLDA is a synchronous input and must not transition during its specified set-up time. There is an implied hold time (HLDA inactive) of TCH from the rising edge of CLK, during which time HLDA must not transition. |
| DREQO- DREQ3 | 16-19 | I | DMA REQUEST: The DMA Request (DREQ) lines are individual asynchronous channel request inputs used by peripheral circuits to obtain DMA service. In Fixed Priority, DREQO has the highest priority and DREQ3 has the lowest priority. A request is generated by activating the DREQ line of a channel. DACK will acknowledge the recognition of a DREQ signal. Polarity of DREQ is programmable. RESET initializes these lines to active high. DREQ must be maintained until the corresponding DACK goes active. DREQ will not be recognized while the clock is stopped. Unused DREQ inputs should be pulled High or Low (inactive) and the corresponding mask bit set. |
| DBO-DB7 | 21-23 26-30 | 1/0 | DATA BUS: The Data Bus lines are bidirectional three-state signals connected to the system data bus. The outputs are enabled in the Program condition during the l/0 Read to output the contents of a register to the CPU. The outputs are disabled and the inputs are read during an l/0 Write cycle when the CPU is programming the 82C37A control registers. During DMA cycles, the most signifi- cant 8-bits of the address are output onto the data bus to be strobed into an externallatch by ADSTB. In memory-to-memory operations, data from the memory enters the 82C37A on the data bus during the read-from-memory transfer, then during the write-to-memory transfer, the data bus outputs write the data into the new memory location. |
| IOR | 1 | I/O | 1/0 READ: l/0 Read is a bidirectional active low three-state line. In the Idle cycle, it is an input con- trol signal used by the CPU to read the control registers. In the Active cycle, it is an output control signal used by the 82C37A to access data from the peripheral during a DMA Write transfer. |
| IOW | 2 | I/O | 1/0 WRITE: 1/0 Write is a bidirectional active low three-state line. In the Idle cycle, it is an input con- trol signal used by the CPU to load information into the 82C37A. In the Active cycle, it is an output control signal used by the 82C37A to load data to the peripheral during a DMA Read transfer. |
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The 3050 has a built-in diode network at the input to pro- tect the circuFt from DC overloading. If the circuit is to respond to very large AC voltages at the input, yet the input threshold is to be a relative low level, the capaci- tor connected between pin 8 and ground helps to stabi- lize the internal regulated voltage and therefore makes the circuit capable of absorbing very large AC signals at the input.
