STLVDS105BD Datasheet The M5M5T5636UG is a family of 18M bit synchronous SRAMs organized as 524288-words by 36-bit. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Mitsubishi's SRAMs are fabricated with high performance, low power CMOS technology, providing greater reliability. M5M5T5636UG operates on 2.5V power/ 1.8V I/O supply or a single 2.5V power supply and are 2.5V CMOS compatible. STLVDS105BD Price| PARAMETER | bYMBOL | bUBGROUPS | MIN | TYP | MAX | UNITS | | Read Cycle Time -20 -25 -30 | tRC | 9. 10, 11 | 20 25 30 | | | ns | | Address Access Time -20 -25 -30 | tAA | 9. 10, 11 | | | 20 25 30 | ns | | Chip Select to Output -20 -25 -30 | tco | 9. 10, 11 | | | 20 25 30 | ns | | Output Enable to Output -20 -25 -30 | tOE | 9. 10, 11 | | | 10 12 14 | ns | | Output Enable to Low-Z Output -20 -25 -30 | tOLZ | 9. 10, 11 | | 0 0 0 | | ns | | Chip Enable to Low-Z Output -20 -25 -30 | tLZ | 9. 10, 11 | | 3 3 3 | | ns | | Output Disable to High-Z Output -20 -25 -30 | tOHZ | 9. 10, 11 | | 5 6 8 | | ns | | Chip Disable to High-Z Output -20 -25 -30 | tHZ | 9. 10, 11 | | 5 6 8 | | ns | | Output Hold from Address Change -20 -25 -30 | tOH | 9. 10, 11 | 3 3 3 | | | ns | | | | | | | |
| | | | | | | | ln peakL | | | | | | | | | | | j | k | j | | IC IIHX | | | | | | | | | | | | | | | | | | | | | ~IX | | | | | | | \Tqp | | | | | | | | | f | | | | | | | | | | | | | | | | | | | | | | | | | | | | Collector to Emittor Voltag~,VO! - v | | | | | | | | |
|
