| Symbol | Pin Name | Description |
| VDD1 | Logic power supply | 2.7 - 3.6 V |
| VDD2 | Driver power supply | 5.0 - 8.0 V |
| VSS1 | Logic ground | Ground(O V) |
| VSS2 | Driver ground | Ground(O V) |
| Y1 - Y384 | Driver outputs | The D/A converted 64 gray-scale analog voltage is output. |
| D0<0:5> - D5<0:5> | Display data input | The display data is input with a width of 36 bits, gray-scale data (6 bits) by 6 dots (R,G,B) DXO: LSB, DX5: MSB |
| SHL | Shift direction control input | This pin controls the direction of shift register in cascade connection. The shift direction of the shift registers is as follows. SHL = H: Dl01 input, Y1} Y384, D102 0utput SHL = L: D102 input, Y384} Y1, Dl01 0utput |
| Dl01 | Start pulse input / output | SHL = H: Used as the start pulse input pin SHL = L: Used as the start pulse output pin |
| D102 | Start pulse input / output | SHL = H: Used as the start pulse output pin SHL = L: Used as the start pulse input pin |
| DATPOL | Data inversion input | DATPOL = H: Display data is inverted DATPOL = L: Display data is not inverted Detects H or L at rising edge of every CLK2. |
| POL | Polarity input | POL = H: The reference voltage for odd number outputs are VGMAl - VGMA5 and those for even number outputs are VGMA6 - VGMA10 POL = L: The reference voltage for odd number outputs are VGMA6 - VGMA10 and those for even number outputs are VGMAl - VGMA5 |
| CLK2 | Shift clock input | Refer to the shift register's shift clock input. The display data is loaded to the data register at the rising edge of CLK2. |
| CLK1 | Latch input | Latches the contents of the data register at rising edge and transfers them to the D/A converter. Also, after CLKl input, clears the internal shift register contents. After l pulse input on start, operates normally. CLKl input timing refers to the "Relationships between CLKl start pulse (DI01, D102) and blanking period" of the switching characteristic waveform. Outputs the gray-scale data at falling edge. |
| VGMA1 VGMA10 | Gamma corrected power supplies | Input the gamma corrected power supplies from external source. VDD2 > VGMAl > VGMA2 > ......... > VGMA9 > VGMA10 > VSS2 Keep gray-scale power supply unchanged during the gray-scale voltage output. |
| TEST | Test input | TEST = L: Normal operation mode TEST = H: Test mode (OP AMP CUT-OFF, Rpd = 15kQ) |
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