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SKKD81-16E Datasheet

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SKKD81-16E Price
The MAX1162 includes an input track-and-hold (T/H) and successive-approximation register (SAR) circuitry to convert an analog input signal to a digital 16-bit out- put. Figure 4 shows the MAX1162 in its simplest config- uration. The serial interface requires only three digital lines (SCLK, CS, and DOUT) and provides an easy interface to microprocessors (UPs). The MAX1162 has two power modes: normal and shut- down. Driving CS high places the MAX1162 in shut- down, reducing the supply current to O.1UA (typ), while pulling CS low places the MAX1162 in normal operating mode. Falling edges on CS initiate conversions that are driven by SCLK. The conversion result is available at DOUT in unipolar serial format. The serial data stream consists of eight zeros followed by the data bits (MSB first). Figure 3 shows the interface timing diagram.
SKKD81-16E on stock

SYMBOL PARAMETER MIN TYP. MAX UNIT NOTES
tPROG Average Programming Time 200 700 US
N Number of Programming Cycles on Same Page (per 512+16 bytes) 2 (1)
tBERASE Block Erasing Time 2 4 ms


that is less than or equal to it. For greater precision, the value of RSET may also be calculated using the ILIM RSET product found in the chart "RSET coeffi- cient vs. ILIM". The maximum current is derived by multiplying the typical current for the chosen RSET in the chart by l.25. A few standard resistor values are listed in the table "Current Limit RSET Values".