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Controlled impedance stripline or microstrip construc- tion must be used to preserve the quality of the signal into the next component and to minimize reflections back into the receiver. Excessive ringing due to reflec- tions caused by improperly terminated signallines makes it difficult for the component receiving these sig- nals to decipher the proper logic levels and may cause transitions to occurwhere none were intended. Also, by minimizing high frequency ringing due to reflections caused by improperly designed and terminated signal lines, possible EMI problems can be avoided. The applications sections in the Signetics ECL 10K/100K Data Manual or the National Semiconductort ECL Logic Databook and Design Guide provide excellent design information on ECL interfacing.
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