| | virTv | |
| wrxclk | ln | 90MHz receive byte clock. The Core samples all Utopia Receive signals on rxclk rising edge. |
| wrxdata[15:0] | Out | Receive data bus. |
| wrxprty (0) | Out | Receive data bus parity. Standard odd or non standard even parity can be optionally generated by the Utopia Slave Core. When the parity generation is disabled during the Core configuration, the pin rxprty can be let unconnected. |
| wrxsoc | Out | Receive start of cell. Asserted to indicate that the current word is the first word of a cell. |
| wrxenb | ln | Active low transmit data transfer enable. |
| wrxclav[0] | Out | Cell buffer available. Asserted in octet level transfers to indicate to the Master that the FIFO is almost empty (Active low) or, in cell level transfers, to indicate to the Master that the PHY port FIFO has space one cell available in the FIFO. |
| wrxclav[3:1] (0) | Out | Extra FIFO Full / Cell buffer available. In MPHY mode and when direct status indication is selected, one rxclav signal is implemented per PHY port. The maximum number of clav signals is limited to four. |
| wrxaddr(4:0) | ln | Utopia receive address. When the Core operates in MPHY mode, address bus used during polling and slave port selection. Bit 4 is the MSB. txaddr(4:0) becomes optional (And should be left open) when the Core does not operate in MPHY mode. |
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