The EM847x includes decryption logic and supports DVD-Video CSS proce- dural specifications. It also fully supports DVD-Video control features includ- ing up t0 8 language sound tracks, 32 subtitle settings, letterbox, pan and scan, multi-angles and 3:2 pull-down.
SKIIP1403GB121-2DW Price| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| F1 | FO | CM | MA | lA | FF | B7 | DL | Function |
| 0 0 1 1 | O 1 O 1 | | | | | | | MCLK = 512 kHz MCLK = 1.536 MHz MCLK = 2.048 MHz MCLK = 2.560 MHz |
| | | 0 1 | | | | | | Linear code Companded code |
| | | | | | | | | Linear Code | Companded Code |
| 0 0 1 1 | O 1 0 1 | 2-complement * sign and magnitude 2-complement 1-complement | MU-Iaw: CCITT D3-D4 * MU-Iaw: Bare Coding A-Iaw including even bit inversion A-Iaw: Bare Coding |
| | | | | | O 1 | | | B1 and B2 consecutive * (1) B1 and B2 separated (1) |
| | | | | | | 0 1 | | 8 bits time-slot * (1) 7 bits time-slot (1 ) |
| | | | | | | | 0 1 | Normal operation Digital Loop-back |
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SKIIP1403GB121-2DW on stock| Characteristic | Symbol | Rating | Unit |
| j L·- | VCBO | - 50 | V |
| j 114t·- | V CEO | - 50 | V |
| I -· | VEBO | -5 | V |
| j p | Ie | - 50 | mA |
| I i y | IE | 50 | mA |
| j p | Pc | 200 | mW |
| | Tj | 125 | oc |
| | Tstg | -55125 | oC |
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| P2.O-P2.1 | 6.7 7 6 | I/0 O l | Port 2: Port 2 is a 2-bit l/0 port with a user-configurable output type. Port 2 latches are configured in the quasi-bidirectional mode and have either ones or zeros written to them during reset, as determined by the PRHI bit in the UCFGl configuration byte. The operation of port 2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section on l/0 port configuration and the DC Electrical Characteristics for details. Port 2 also provides various special functions as described below. P2.0 X2 0utput from the oscillator amplifier (when a crystal oscillator option is selected via the EPROM configuration). CLKOUT CPU clock divided by 6 clock output when enabled via SFR bit and in conjunction with internal RC oscillator or external clock input. P2.1 X1 Input to the oscillator circuit and internal clock generator circuits (when selected via the EPROM configuration). |
| Vss | 5 | l | Ground: 0 V reference. |
| VDD | 15 | l | Power Supply: This is the power supply voltage for normal operation as well as Idle and Power Down modes. |
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