| Pin Number | Symbol | Name/Description | Logic Family |
| Receiver |
| MS | MS | Mounting Studs. The mounting studs are provided for transceiver mechani- cal attachment to the circuit board. They may also provide an optional con- nection of the transceiver to the equipment chassis ground. | NA |
| 1 | Photode- tector Bias | Photodetector Bias. This lead supplies bias for the PIN photodetector diode. | NA |
| 2 | VEER | Receiver Signal Ground. | NA |
| 3 | VEER | Receiver Signal Ground. | NA |
| 4 | CLK- | Received Recovered Clock Out. The rising edge occurs at the rising edge of the received data output. The falling edge occurs in the middle of the received data bit period. | PECL |
| 5 | CLK+ | Received Recovered Clock Out. The falling edge occurs at the rising edge of the received data output. The rising edge occurs in the middle of the received data bit period. | PECL |
| 6 | VEER | Receiver Signal Ground. | NA |
| 7 | VCCR | Receiver Power Supply. | NA |
| 8 | SD | Signal Detect. Normal operation: logic one output. Fault condition: logic zero output. | LVTTL |
| 9 | RD- | Received DATA Out. No internal terminations will be provided. | PECL |
| 1 0 | RD+ | Received DATA Out. No internal terminations will be provided. | PECL |
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