DAC register address this PROM array. Thus for every com- bination of the primary DAC's most significant bits a different C-DAC code is selected, allowing correctino of superposition erros. These errors are cuased by bit interaction on the pri- mary ladder's current bus and by voltage non-linearity in the feedback resistor. Superposition errors cannot be corrected by any method that corrects individual bits only, such as laser trimming.
SK8051 on stock| Pin | Symbol | unction | Configuration |
| 1 | CLK | Clock output signal for micro con roller The clock output frequency is set by the crystal to fx rAL/4 | |
| 2 | PA_ENABLE | Switches on power amplifier, used for ASK modulation | PAENABLE 50k ~~_Ol,lV |
| 3 4 | ANT2 ANT1 | Emitter of antenna output stage Open collector antenna output | ^-_J > -l 2 > |
| 5 | XTAL | Connection for crystal | VS VS |
| 6 | VS | Supply voltage | See ESD protection circuitry (see Figure 8 0n page 8) |
| 7 | GND | Ground | See ESD protection circuitry (see Figure 8 0n page 8) |
| 8 | ENABLE | Enable input | ENABLE nt..i. - |
| | | |
| SYMBOL | PARAMETER | CONDITIONS | MIN | TYP | MAX | UNIT |
| Viso, | R.M.S. isolation voltage from all three terminals to external heatsink | f = 50-60 Hz; sinusoidal wavefo rm; R.H. " 65% ; clean and dustfree | | | 2500 | V |
| Ciso, | Capacitance from T2 to external heatsink | f=l MHz | | 1 0 | | pF |
| | | | | | |
