| No | Name | Type | Description |
| PCI Bus Interface |
| 121- 124,127- 12 8,1- 2,5,7- 9,11- 14,27- 32,3 5- 36,38,39- 40,42-46 | AD31-0 | I/O | Address/Data are multiplexed on the same PCI pins. A bus transaction consists of an address phase followed by one or more data phases. The address phase is the clock cycle in which FRAME# is asserted. Write data is stable and valid when IRDYB is asserted and read data is stable and valid when TRDYB is asserted. |
| 115 | PCICLK | I | PCICLK provides timing for all transactions on PCI and is an input pin to every PCI device. |
| 113 | INTA# | OD | INTA# is an asynchronous signal which is used to request an interrupt |
| 114 | PCIRST# | I | When PCIRST# is asserted low, the VT86C100A chip performs an internal system hardware reset. PCIRST# may be asynchronous to CLK when asserted or deasserted. It is recommended that the deassertion be synchronous to guarantee clean and bounce free edge. |
| 3,16,26,37 | CBE#[3:0] | I | Bus Command/Byte Enables are multiplexed on the same PCI pins. During the address phase of a transaction, CBE3-OB define the Bus Command. Burring the data phase, CBE3-OB are used as Byte Enables. The Byte Enables define which physical byte lanes carry meaningful data. CBEOB applies to byte o and CBE3B applies to byte 3. |
| 4 | IDSEL | I | Used as a chip select during PCI configuration cycle. |
| 17 | FRAME# | I/O | Cycle Frame is driven by the current master to indicate the beginning and duration of an access. FRAME# is asserted to indicate a bus transaction is beginning. While FRAME# is asserted, data transfers continue. When FRAME# is deasserted, the transaction is in the final data phase. |
| 18 | IRDY# | I/O | Initiator Ready indicates the initiating agent's ability to complete the current data phase ofthe transaction. IRDY# is used in conjunction with TRDY#. A data phase is completed on any clock when both IRDY# and TRDY# are asserted. During a write, IRDY# indicates that valid data is present on AD31-0. During a read, it indicates the master is prepared to accept data. Wait cycles are inserted until both IRDY# and TRDY# are asserted simultaneously. |
| 19 | TRDY# | I/O | Target Ready indicates the target's agent's ability to complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. A data phase is completed on any clock when both IRDY# and TRDY# are asserted. During a read, TRDY# indicates that valid data is present on AD31-0. During a write, it indicates the target is prepared to accept data. Wait cycles are inserted until both IRDY# and TRDY# are asserted simultaneously. |
| 20 | DEVSEL# | I/O | Device Select, when actively driven, indicates the driving device has decoded its address as the target of the current access. As an input, DEVSEL# indicates whether any device on the bus has been selected. |
| 21 | STOP# | I/O | VT86C100A drives STOP# to disconnect further traction. |
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