ADMap-9  > SK23-T1

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SK23-T1 Datasheet
Include 6.8yF and O.OlyF ceramic capacitors Place the 6.8yF capacitor within 0.75 inches of the power pin Place the O.OlyF capacitor within O.l inches of the power pin Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance Minimize all trace lengths to reduce series inductances
SK23-T1 Price
cuits-traditionally found in incandescent multiplexed display systems are eliminated. It also allows low strobing rates to be used without display flicker. Another DM9370 feature is the reduced loading on the data inputs when the Latch Enable is HIGH (only 10 ccA typ). This allows many DM9370s to be driven from a MOS device in multiplex mode without the need for drivers on the data lines. The DM9370 also provides automatic blank- ing of the leading and/or trailing-edge zeroes in a multidigit decimal number, resulting in an easily readable decimal display conforming to normal writing practice. In an 8-digit mixed integer fraction decimal representation, using the automatic blanking capability, 0060.0300 would be dis- played as 60.03. Leading-edge zero suppression is obtained by connecting the Ripple Blanking Output (RBO) of a decoder to the Ripple Blanking Input (RBI) of the next lower stage device. The most significant decoder stage should have the RBI input grounded; and since suppres- sion of the least significant integer zero in a number is not usually desired, the RBI input of this decoder stage should be left open. A similar procedure for the fractional part of a display will provide automatic suppression of trailing-edge zeroes. The RBO terminal of the decoder can be OR-tied
SK23-T1 on stock

PARAMETER SYMBOL MIN MAX UNITS
Supply Voltage, dc, Clock Buffers (Vss = ground) AVoo Vss - 0.5 7 V
Supply Voltage, dc, Core VDD Vss - 0.5 7 V
Input Voltage, dc VI Vss - 0.5 VDD+ 0.5 V
Output Voltage, dc Vo Vss - 0.5 VDD+ 0.5 V
Input Clamp Current. dc (Vi < 0 0r V, > Voo) JlK -50 50 mA
Output Clamp Current. dc (Vi < 0 0r V, > VDD) IOK -50 50 mA
Storage Temperature Range (non-condensing) Ts -65 150 ac
Ambient Temperature Range, Under Bias TA -55 125 ac
Junction Temperature TJ 125 ac
Lead Tem perature (soldering, 1 0s) 260 ac
Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7) 2 kV


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