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SK025M0022B2F-0511 Datasheet

Model Tem perature Range P ackage Option'
AD9057BRS-40, -60, -80 AD9057/PCB -40IC to +85IC +25 YC RS-20 Evaluation Board


SK025M0022B2F-0511 Price

Pin unction Description Interface Schematic
24 PD Power Down Control. When logic "high" (>Vcc-0.3V), all circuits are


SK025M0022B2F-0511 on stock

Vcc =4.OVdc
1i TA = 27"C T2 pin = - 4 (lrl R m
II1- 0 tUUUll l l l
l j l l l
I - J _ { } II 5dBm
iiiil I I
-20dBm I I I II ) I I
L -5clBm IIIII


NOTES: 1. See RECOMMENDED OPERATING RANGE table. 2. For 2.5V LVTTL single-ended operation, the RxS pin is tied HIGH and ANREF is tied to GND. 3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR iS the "true" input level and VCP iS the "complement" input level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching to a new state. 4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only. 5. For single-ended operation, in differential mode, ANREF is tied to the DC voltage VREF. 6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode. 7. Voltage required to maintain a logic LOW, single-ended operation in differential mode. 8. Typical values are at VDD = 2.5V, VDDO = VDD, +250C ambient. 9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be referenced. 10. For differential mode (RxS = LOW), A and ANREF must be at the opposite rail.