| Parameter | Name | Description | Min | Typ. | Max | Unit |
| tl | Output Frequency | 30-pF load 10-pF load | 10 10 | | 100 133.33 | MHz MHz |
| | Duty Cycle[6J = t2 Xl ti | Measured at l.4V, Fout = 66.67 MHz | 40.0 | 50.0 | 60.0 | % |
| | Duty Cycle[6J = t2 -X/ ti | Measured at l.4V, Fout < 50.0 MHz | 45.0 | 50.0 | 55.0 | % |
| t3 | Rise Time[6l | Measured between 0.8V and 2.OV | | | 1.50 | ns |
| t4 | Fall Time[6J | Measured between 0.8V and 2.OV | | | 1.50 | ns |
| t5 | Output to Output Skew[6l | All outputs equally loaded | | | 250 | ps |
| t6A | Delay, REF Rising Ed9c~ to CLKOUT Rising Edger61 | Measured at VDD/2 | | 0 | +350 | ps |
| t6B | Delay, REF Rising Edge to CLKOUT Rising ~dgef6J | Measured at VDD/2. Measured in PLL Bypass Mode, CY2309 device only. | 1 | 5 | 8.7 | ns |
| t7 | Device to Device Skew[6l | Measured at VDD/2 0n the CLKOUT pins of devices | | 0 | 700 | ps |
| t8 | Output Slew Rate[6J | Measured between 0.8V and 2.OV using Test Circuit #2 | 1 | | | V/ns |
| tJ | Cycle to Cycle Jitter[6J | Measured at 66.67 MHz, loaded outputs | | | 200 | ps |
| tLOCK | PLL Lock Time[6J | Stable power supply, valid clock presented on REF pin | | | 1.0 | ms |
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