SJE5527 Datasheet| Pin No. | Mnemonic | In/Out | Description | | 1 2, 3, 4 5, 6, 7 8, 9, 10 11, 12, 13 14 15 16 17 18 19 20 21 23 24 25 26 27, 28, 29 30, 31, 32 33, 34, 35 36, 37, 38 39, 40, 41, 42 43, 45, 48, 49 44 46 47 50, 51, 52 | PGND1 OUTA PVDD1 OUTB PGND1 ERR3 ERR2 ERR~ ERRO INA INB DVDD DGND MUTE INC IND RST/PDN CLK PGND2 OUTD PVDD2 OUTC PGND2 AGND MODEO AVDD MODE1 PGND1 | O O I/O I/O I/O I/O I I I I I I I O O I | Negative power supply for high power Transistors A2 and B2. Output of transistor pair Al and A2. Positive power supply for high power Transistors Al and Bl. Output of transistor pair Bl and B2. Negative power supply for high power Transistors A2 and B2. Edge speed setting MSB during RESET/active low thermal shutdown error output during normal operation. Edge speed setting Bit l during RESET/active low thermal warning error output during normal operation. Nonoverlap time setting MSB during RESET/active thermallow shutdown error output during normal operation. Nonoverlap time setting Bit l during RESET/active low data-loss error output or low-side transistor disable input during normal operation. Control pin for Transistors Al and A2 always; also control pin for Bl and B2 in 2-channel mode. Edge speed setting LSB during RESET/during normal operation, control pin for Transistors Bl and B2 in 4-channel mode, no function in 2-channel mode. Positive power supply for low power digital circuitry. Negative power supply for low power digital circuitry. Active low clickless mute input. Control pin for Transistors Cl and C2 always, also control pin for Dl and D2 in 2-channel mode. Nonoverlap time setting LSB during RESET/during normal operation, control pin for Transis- tors Dl and D2 in 4-channel mode; no function in 2-channel mode. Active low RESET/power-down input. External clock input in external clock mode. Negative power supply for high power Transistors C2 and D2. Output of transistor pair Dl and D2. Positive power supply for high power Transistors Cl and Dl. Output of transistor pair Cl and C2. Negative power supply for high power Transistors C2 and D2. Negative power supply for low power analog circuitry. Clock source select (referenced to AGND); normally connected to AGND. Positive power supply for low power analog circuitry. Channel mode select (referenced to AGND). Negative power supply for high power Transistors A2 and B2. | | | | |
SJE5527 Price 6. Supplement 1) Ihis infiared detecting unit for remote control satisfies each performance requirements in para 3.5, in the standard optical system in Fig.2. 2) This productis built-inphotodiode. 3) Productmass: Approx.0.7g 4) This product shallnot contain ffie following materials. Also, ffie following materials shall not be used in the production process for this product Mata'ials for ODS : CFCs, Halon, Carbon tetrachloride, l.l.l-Trichloroethane (Methyl chloroform) 5) Batedflameretardants Speci~c brominated flame retardants such as the PBBOs and PBBs are not used in this device at all. 6) Packing specification : Refer to the attached sheet, Page 11. 7) Comtryoforigin: Phijillpine,Indonesia SJE5527 on stock| Symbol | Min | Typ | Max | | A | 0.90 | O95 | 1.00 | | A1 | 0.30 | 0.35 | 0.40 | | E | | 11.00 | | | E1 | | 6.40 | | | D | | 8.00 | | | Di | | 6.40 | | | e | | O80 | | | b | 0.40 | 0.45 | 0.50 | | z | | | O10 | | | | |
Note l: AVDD = +5V, AVSS = -5V, DVDD = +5V, VREFIN = 2.500V (external), Virxi = +5V (MAX115) or +2.5V (MAX116). Note 2: Integral nonlinearity is the analog value's deviation at any code from its theoretical value after the full-scale range and offset have been calibrated.
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